XR16C864IQ-F Exar Corporation, XR16C864IQ-F Datasheet - Page 13

• Manufacturer Part Number: XR16C864IQ-F
• Description: IC UART FIFO 128B QUAD 100QFP
• Manufacturer: Exar Corporation
• Type: Quad UART with 128-byte FIFOsr

Specifications of XR16C864IQ-F

• Number Of Channels: 4, QUART
• Package / Case: 100-BQFP
• Features: *
• Fifo's: 128 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 3 mA to 6 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.97 V to 5.5 V
• No. Of Channels: 4
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1277

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REV. 2.0.1
frequencies are: 1.8432, 3.6864, 7.3728, 14.7456, 18.432, and 22.1184 MHz. Alternatively, an external clock
can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates.
Typical oscillator connections are shown in
application note DAN108 on EXAR’s web site.
Each UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by a
software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input crystal or external
clock by 1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides this clock by a
programmable divisor between 1 and (2
sampling rate clock is used by the transmitter for data bit shifting and receiver for data sampling.
Table 6 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling
rate. When using a non-standard frequency crystal or external clock, the divisor value can be calculated for
DLL/DLM with the following equation.
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 128 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
O
2.11
2.12
UTPUT
MCR Bit-7=1
115.2k
230.4k
19.2k
38.4k
57.6k
1200
2400
4800
9600
100
600
Programmable Baud Rate Generator
Data Rate
Transmitter
F
IGURE
T
ABLE
X T A L1
X T A L2
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16)
O
UTPUT
5. B
6: T
MCR Bit-7=0
(D
153.6k
230.4k
460.8k
921.6k
EFAULT
19.2k
38.4k
76.8k
YPICAL DATA RATES WITH A
2400
4800
9600
400
AUD
Data Rate
R
C ry s ta l
B u ffer
)
O s c /
ATE
G
Clock (Decimal)
D
ENERATOR AND
IVISOR FOR
16
2304
-1) to obtain a 16X sampling rate clock of the serial data rate. The
384
192
96
48
24
12
6
4
2
1
D iv id e b y 4
D iv id e b y 1
P re s ca le r
P re s ca le r
Figure
16x
14.7456 MH
P
4. For further reading on oscillator circuit please see
D
13
RESCALER
IVISOR FOR
Clock (HEX)
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
M C R B it-7 = 0
M C R B it-7 = 1
(d e fa ult)
900
180
C0
0C
60
30
18
06
04
02
01
Z CRYSTAL OR EXTERNAL CLOCK
16x
B a u d R a te
D L L an d D L M
G e n era to r
R e g iste rs
L o g ic
V
ALUE
P
ROGRAM
DLM
09
01
00
00
00
00
00
00
00
00
00
(HEX)
R a te C lo c k to
T ra n sm itte r
S a m plin g
1 6 X
V
ALUE
P
ROGRAM
DLL
C0
0C
00
80
60
30
18
06
04
02
01
(HEX)
XR16C864
D
E
ATA
RROR
0
0
0
0
0
0
0
0
0
0
0
R
ATE
(%)