XR16C864IQ-F Exar Corporation, XR16C864IQ-F Datasheet
XR16C864IQ-F
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XR16C864IQ-F Summary of contents
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APRIL 2004 GENERAL DESCRIPTION 1 The XR16C864 (864 enhanced quad Universal Asynchronous Receiver and Transmitter (UART) each with 128 bytes of transmit and receive FIFOs, transmit and receive FIFO counters and trigger levels, automatic hardware and software flow ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO F 2. XR16C864 IGURE IN UT SSIGNMENT TXRDYD#/TXDRQD 81 RXRDYD#/RXDRQD 82 CDD# 83 RID# 84 RXD 85 VCC 86 INTSEL ...
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... REV. 2.0.1 ORDERING INFORMATION P N ART UMBER XR16C864CQ 100-Lead QFP XR16C864IQ 100-Lead QFP PIN DESCRIPTIONS Pin Description 100-QFP N T AME YPE DATA BUS INTERFACE Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channels A-D during a data bus transaction ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO Pin Description 100-QFP N T AME YPE CSD When 16/68# pin is at logic 1, this input is chip select D (active low) to enable channel ...
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REV. 2.0.1 Pin Description 100-QFP N T AME YPE Direct Memory Access Terminal Count. A high pulse terminates a Direct Memory Access transaction. If Direct Memory Access is not used, ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO Pin Description 100-QFP N T AME YPE DTRA UART channels A-D Data-Terminal-Ready (active low) or general purpose output. If these outputs are not used, leave them ...
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REV. 2.0.1 Pin Description 100-QFP N T AME YPE CHCCLK 42 I This input provides the clock for UART channel C. An external 16X baud clock or the crystal oscillator’s output, XTAL2, must ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO 1.0 PRODUCT DESCRIPTION The XR16C864 (864) integrates the functions of 4 enhanced 16C550 Universal Asynchronous Receiver and Transmitter (UART). Each UART is independently controlled having its own set of device configuration ...
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REV. 2.0.1 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The 864 data interface supports ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO 2.2 5-Volt Tolerant Inputs For devices that have top mark date code "F2 YYWW" and newer, the 864 can accept a voltage 5.5V on any of its inputs ...
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REV. 2.0 2.6 Channels A-D Internal Registers Each UART channel in the 864 has a set of enhanced registers for control, monitoring and data loading and unloading. The configuration ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO 2.8 Direct Memory Access In this document, Direct Memory Access will not be referred to by its acronym (DMA) to avoid confusion with DMA Mode (a legacy term) that refers to ...
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REV. 2.0.1 frequencies are: 1.8432, 3.6864, 7.3728, 14.7456, 18.432, and 22.1184 MHz. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates. Typical ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the TX FIFO and TSR are reported in the Line Status Register (LSR bit-5 and bit-6). 2.12.1 Transmit ...
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REV. 2.0.1 2.13 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and 128 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO IGURE ECEIVER PERATION IN 16X Clock Receive Data Shift Register (RSR) 128 bytes by 11-bit wide FIFO Receive Data Byte and Errors N : Table-B selected as ...
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REV. 2.0.1 Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the CTS# pin is de-asserted (logic 1): ISR bit-5 will be set to 1, and UART will suspend ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO Xoff characters (See Table 17) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected, the 864 compares two consecutive receive characters with two software flow control 8-bit values (Xon1, Xon2, ...
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REV. 2.0.1 infrared modules on the market which indicate a logic light pulse. So the 864 has a provision to invert the input polarity to accomodate this. In this case, user can enable ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while an interrupt is pending in any channel. The 864 will ...
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REV. 2.0 IGURE NTERNAL Transmit Shift Register Receive Shift Register 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO B C A-D OOP ACK IN HANNELS VCC (THR/FIFO) MCR bit-4=1 (RHR/FIFO) VCC RTS# ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO 3.0 UART INTERNAL REGISTERS Each UART channel in the 864 has its own set of configuration registers selected by address lines A0, A1 and A2 with a specific channel selected (See ...
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REV. 2.0 INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR Bit-7 ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO T 9: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE DLL RD/WR Bit DLM ...
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REV. 2.0.1 4.0 INTERNAL REGISTER DESCRIPTIONS 4.1 Receive Holding Register (RHR) - Read- Only See “Receiver” on page 15. 4.2 Transmit Holding Register (THR) - Write-Only See “Transmitter” on page 13. 4.3 Interrupt Enable Register (IER) ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO IER[3]: Modem Status Interrupt Enable Logic 0 = Disable the modem status register interrupt (default). Logic 1 = Enable the modem status register interrupt. IER[4]: Sleep Mode Enable (requires EFR[4] = ...
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REV. 2.0 ABLE P ISR R RIORITY EGISTER EVEL ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO FCR[2]: TX FIFO Reset This bit is only active when FCR bit ‘1’. Logic transmit FIFO reset (default). Logic 1 = Reset the transmit FIFO pointers ...
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REV. 2.0.1 T 11: T ABLE RANSMIT AND FCTR FCTR FCR FCR FCR ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length. BIT LCR[3]: TX and ...
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REV. 2.0.1 LCR[7]: Baud Rate Divisors Enable Logic 0 = Data registers are selected (default). Logic 1 = Divisor latch registers are selected. 4.7 Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write The ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO MCR[6]: Infrared Encoder/Decoder Enable Logic 0 = Enable the standard modem receive and transmit input/output interface (default). Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are ...
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REV. 2.0.1 LSR[6]: THR and TSR Empty Flag This bit is set to a logic 1 whenever the transmitter goes idle set to logic 0 whenever either the THR or TSR contains a data ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO MSR[7]: CD Input Status CD# (active high, logical 1). Normally this bit is the compliment of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the ...
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REV. 2.0.1 EMSR[5:4]: Extended RTS Hysteresis EMSR EMSR[7:6]: Reserved 4.12 FIFO Level Register (FLVL) - Read-Only The ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO 4.17 FIFO Data Count Register (FC) - Read-Only This register is accessible when LCR = 0xBF. Note that this register is not identical to the FIFO Level Count Register which is ...
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REV. 2.0.1 EFR[3:0]: Software Flow Control Select Single character and dual sequential characters software flow control is supported. Combinations of software flow control can be selected by programming these bits. T ABLE EFR -3 EFR -2 ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO EFR[6]: Auto RTS Flow Control Enable RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is selected, an interrupt will be ...
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REV. 2.0.1 T 18: UART RESET CONDITIONS FOR CHANNELS A-D ABLE REGISTERS DLL DLM RHR THR IER FCR ISR LCR MCR LSR MSR SPR EMSR FLVL TRG FC FCTR EFR XON1 XON2 XOFF1 XOFF2 FSTAT I/O ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (100-QFP) DC ELECTRICAL CHARACTERISTICS O U ...
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REV. 2.0.1 AC ELECTRICAL CHARACTERISTICS TA (-40 + FOR INDUSTRIAL GRADE PACKAGE S P YMBOL ARAMETER CLK Clock Pulse Duration OSC Oscillator Frequency OSC External Clock Frequency ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO AC ELECTRICAL CHARACTERISTICS TA (-40 + FOR INDUSTRIAL GRADE PACKAGE S P YMBOL ARAMETER TSI Delay From Stop To Interrupt TINT Delay ...
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REV. 2.0 IGURE ODE NTEL ATA A0-A7 Valid Address T AS CS# IOR# T RDV D0- IGURE ODE NTEL ATA A0-A7 Valid ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO F 17 IGURE ODE OTOROLA A0-A7 T ADS CS# T RWS R/W# T RDA D0- IGURE ODE OTOROLA A0-A7 ...
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REV. 2.0 & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR & I IGURE RANSMIT EADY NTERRUPT TX Start ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO F 21 & I IGURE ECEIVE EADY NTERRUPT Start Bit RX S D0:D7 S D0:D7 Stop Bit INT T SSR RXRDY# First Byte is Received in RX FIFO IOR# ...
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REV. 2.0 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX S D0:D7 (Unloading) IER[1] ISR is read enabled INT* TX FIFO fills up Data in TX FIFO TXRDY# ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO PACKAGE DIMENSIONS 100 LEAD PLASTIC QUAD FLAT PACK ( QFP, 1.95 mm Form) 81 100 Seating Plane A 1 Note: The control dimension is ...
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... April 2004 Rev. 2.0.1 EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...
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XR16C864 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO GENERAL DESCRIPTION .................................................................................................1 F .....................................................................................................................................................1 EATURES A ................................................................................................................................................1 PPLICATIONS F 1. XR16C864 B D IGURE LOCK IAGRAM F 2. XR16C864 IGURE IN UT SSIGNMENT PIN DESCRIPTIONS .........................................................................................................3 .................................................................................................................................3 ...
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REV. 2.0.1 4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 25 4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION................................................................ 25 4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 26 4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 26 4.4.2 ...