XR21V1412IL32-F Exar Corporation, XR21V1412IL32-F Datasheet - Page 25

IC UART FIFO USB DUAL 32QFN

XR21V1412IL32-F

Manufacturer Part Number
XR21V1412IL32-F
Description
IC UART FIFO USB DUAL 32QFN
Manufacturer
Exar Corporation
Type
USB UARTsr
Datasheet

Specifications of XR21V1412IL32-F

Package / Case
32-VFQFN Exposed Pad
Features
*
Number Of Channels
2, DUART
Fifo's
128 Byte, 384 Byte
Protocol
USB 2.0
Voltage - Supply
2.97 V ~ 3.63 V
With Auto Flow Control
Yes
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Current
16 mA
Operating Supply Voltage
2.97 V to 3.63 V
No. Of Channels
2
Data Rate
12Mbps
Uart Features
Automatic Hardware And Software Flow Control, Half-Duplex Mode, Fractional Baud Rate Generator
Supply Voltage Range
2.97V To 3.63V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
1016-1301 - EVAL BOARD FOR XR21V1412IL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
1016-1302

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XR21V1412IL32-F
Manufacturer:
EXAR
Quantity:
1 800
Part Number:
XR21V1412IL32-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
REV. 1.1.0
This register is automatically set to logic ’1’ for baud rates below 46921 bps, and can be manually set for baud
rates of 46921 bps and higher. This register enables the Low latency feature of the UART. Write to this
register following any desired baud rate setting change.
LOW_LATENCY[0]: Enable Low Latency mode
LOW_LATENCY[7:1]: Reserved
These bits are reserved and should remain ’0’.
This register is used to enable / disable GPIO status in the high data byte of the custom interrupt packet. See
Table 16, “Interrupt Packet Format,” on page 26 and Table 18, “Data Field of Customized Interrupt Packet -
Exar Vendor Specific,” on page 27.
CUSTOM_INT_PACKET[0]: GPIO1
CUSTOM_INT_PACKET[1]: GPIO2
CUSTOM_INT_PACKET[2]: Reserved
CUSTOM_INT_PACKET[3]: GPIO0
CUSTOM_INT_PACKET[4]: GPIO3
CUSTOM_INT_PACKET[5]: GPIO4
CUSTOM_INT_PACKET[6]: GPIO5
CUSTOM_INT_PACKET[7]: Reserved
This bit is reserved and should remain ’0’.
3.4.2
3.4.3
Logic 0 = Receive data is not forwarded from the Rx FIFO until bMaxPacketSize (64 bytes) or timeout (3
characters) has occurred.
Logic 1 = All data in the RX FIFO is provided to the USB host at the next BULK IN request irrespective of the
number of bytes in the FIFO.
Logic 0 = Disable GPIO1 status in custom interrupt packet.
Logic 1 = Enable GPIO1 status in custom interrupt packet.
Logic 0 = Disable GPIO2 status in custom interrupt packet.
Logic 1 = Enable GPIO2 status in custom interrupt packet.
This bit is reserved and should remain ’0’.
Logic 0 = Disable GPIO0 status in custom interrupt packet.
Logic 1 = Enable GPIO0 status in custom interrupt packet.
Logic 0 = Disable GPIO3 status in custom interrupt packet.
Logic 1 = Enable GPIO3 status in custom interrupt packet.
Logic 0 = Disable GPIO4 status in custom interrupt packet.
Logic 1 = Enable GPIO4 status in custom interrupt packet.
Logic 0 = Disable GPIO5 status in custom interrupt packet.
Logic 1 = Enable GPIO5 status in custom interrupt packet.
LOW_LATENCY Register Description (Read/Write)
CUSTOM_INT_PACKET (Read/Write)
25
2-CH FULL-SPEED USB UART
XR21V1412

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