SC16C852IBS,151 NXP Semiconductors, SC16C852IBS,151 Datasheet - Page 25

• Manufacturer Part Number: SC16C852IBS,151
• Description: IC UART DUAL W/FIFO 32HVQFN
• Manufacturer: NXP Semiconductors
• Type: IrDAr

Specifications of SC16C852IBS,151

• Number Of Channels: 2, DUART
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Features: Programmable
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 2.5 V ~ 3.3 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Voltage: 1.65 V ~ 1.95 V
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 2.5 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935283099151 SC16C852IBS-S

NXP Semiconductors
SC16C852_1
Product data sheet
7.1 Transmit (THR) and Receive (RHR) Holding Registers
7.2 Interrupt Enable Register (IER)
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the
transmit FIFO. The THR empty flag in the LSR will be set to a logic 1 when the transmit
FIFO is empty or when data is transferred to the TSR.
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a
Receive Serial Shift Register (RSR). Receive data is removed from the SC16C852
receive FIFO by reading the RHR. The receive section provides a mechanism to prevent
false starts. On the falling edge of a start or false start bit, an internal receiver counter
starts counting clocks at the 16 clock rate. After 7
shifted to the center of the start bit. At this time the start bit is sampled, and if it is still a
logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. Receiver status codes will be posted in the LSR.
The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INTA, INTB output pins.
Table 11.
Bit
7
6
5
4
3
2
Symbol Description
IER[7]
IER[6]
IER[5]
IER[4]
IER[3]
IER[2]
Interrupt Enable Register bits description
CTS interrupt.
RTS interrupt.
Xoff interrupt.
Sleep mode.
Modem Status Interrupt. This interrupt will be issued whenever there is a modem
status change as reflected in MSR[3:0].
Receive Line Status interrupt. This interrupt will be issued whenever a receive
data error condition exists as reflected in LSR[4:1].
logic 0 = disable the CTS interrupt (normal default condition)
logic 1 = enable the CTS interrupt. The SC16C852 issues an interrupt when
the CTSA/CTSB pin transitions from a logic 0 to a logic 1.
logic 0 = disable the RTS interrupt (normal default condition)
logic 1 = enable the RTS interrupt. The SC16C852 issues an interrupt when
the RTSA/RTSB pin transitions from a logic 0 to a logic 1.
logic 0 = disable the software flow control, receive Xoff interrupt (normal
default condition)
logic 1 = enable the receive Xoff interrupt
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode
logic 0 = disable the modem status register interrupt (normal default condition)
logic 1 = enable the modem status register interrupt
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
Rev. 01 — 31 August 2009
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
1
2
clocks, the start bit time should be
SC16C852
© NXP B.V. 2009. All rights reserved.
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