SC16C852IBS,151 NXP Semiconductors, SC16C852IBS,151 Datasheet - Page 22

• Manufacturer Part Number: SC16C852IBS,151
• Description: IC UART DUAL W/FIFO 32HVQFN
• Manufacturer: NXP Semiconductors
• Type: IrDAr

Specifications of SC16C852IBS,151

• Number Of Channels: 2, DUART
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Features: Programmable
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 2.5 V ~ 3.3 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Voltage: 1.65 V ~ 1.95 V
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 2.5 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935283099151 SC16C852IBS-S

NXP Semiconductors
7. Register descriptions
SC16C852_1
Product data sheet
6.14.3.2 Auto address detection
If Special Character Detect is enabled (EFR[5] is set and the Xoff2 register contains the
address byte) the receiver will try to detect an address byte that matches the programmed
character in the Xoff2 register. If the received byte is a data byte or an address byte that
does not match the programmed character in the Xoff2 register, the receiver will discard
these data. Upon receiving an address byte that matches the Xoff2 character, the receiver
will be automatically enabled if not already enabled, and the address character is pushed
into the RX FIFO along with the parity bit (in place of the parity error bit). The receiver also
generates a line status interrupt (IER[2] must be set to ‘1’ at this time). The receiver will
then receive the subsequent data from the ‘master’ station until being disabled by the
controller after having received a message from the ‘master’ station.
If another address byte is received and this address byte does not match the Xoff2
character, the receiver will be automatically disabled and the address byte is ignored. If
the address byte matches the Xoff2 character, the receiver will put this byte in the RX
FIFO along with the parity bit in the parity error bit (LSR bit 2).
Table 10
assigned bit functions are more fully defined in
details the assigned bit functions for the SC16C852 internal registers. The
Rev. 01 — 31 August 2009
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
Section 7.1
through
SC16C852
Section
© NXP B.V. 2009. All rights reserved.
7.23.
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