SC68C652BIB48,157 NXP Semiconductors, SC68C652BIB48,157 Datasheet - Page 13

• Manufacturer Part Number: SC68C652BIB48,157
• Description: IC UART DUAL 48LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC68C652BIB48,157

• Features: 2 Channels
• Number Of Channels: 2, DUART
• Fifo's: 32 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-LFQFP
• Voltage: 2.25 V ~ 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935278766157; SC68C652BIB48; SC68C652BIB48

NXP Semiconductors
SC68C652B_2
Product data sheet
6.10 Loopback mode
6.9 DMA operation
Table 6.
The SC68C652B FIFO trigger level provides additional flexibility to the user for block
mode operation. The user can optionally operate the transmit and receive FIFOs in the
DMA mode (FCR[3]). The DMA mode affects the state of the RXRDYn and TXRDYn
output pins.
Table 7.
Table 8.
The internal loopback capability allows on-board diagnostics. In the loopback mode, the
normal modem interface pins are disconnected and reconfigured for loopback internally
(see
In the loopback mode, the transmitter output pin (TXn) and the receiver input pin (RXn)
are disconnected from their associated interface pins, and instead are connected together
internally. The CTSn, DSRn, CDn, and RIn pins are disconnected from their normal
modem control inputs pins, and instead are connected internally to MCR[1] RTS,
Output
baud rate
50
75
110
150
300
600
1200
2400
3600
4800
7200
9600
19.2 k
38.4 k
57.6 k
115.2 k
Non-DMA mode
1 = FIFO empty
0 = at least 1 byte in FIFO
Non-DMA mode
1 = at least 1 byte in FIFO
0 = FIFO empty
Figure
Baud rate generator programming table using a 1.8432 MHz clock
Effect of DMA mode on state of RXRDYn pin
Effect of DMA mode on state of TXRDYn pin
4). MCR[3:0] register bits are used for controlling loopback diagnostic testing.
Table 7
Output
16 clock divisor
(decimal)
2304
1536
1047
768
384
192
96
48
32
24
16
12
6
3
2
1
and
Rev. 02 — 2 November 2009
Table 8
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
show this.
DMA mode
0-to-1 transition when FIFO empties
1-to-0 transition when FIFO reaches trigger level,
or time-out occurs
DMA mode
0-to-1 transition when FIFO becomes full
1-to-0 transition when FIFO goes below trigger level
Output
16 clock divisor
(HEX)
900
600
417
300
180
C0
60
30
20
18
10
0C
06
03
02
01
DLM
program value
(HEX)
09
06
04
03
01
00
00
00
00
00
00
00
00
00
00
00
SC68C652B
© NXP B.V. 2009. All rights reserved.
DLL
program value
(HEX)
00
00
17
00
80
C0
60
30
20
18
10
0C
06
03
02
01
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