78P2351-IGTR/F Maxim Integrated Products, 78P2351-IGTR/F Datasheet - Page 3

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78P2351-IGTR/F

Manufacturer Part Number
78P2351-IGTR/F
Description
LINE INTERFACE UNIT 100-LQFP
Manufacturer
Maxim Integrated Products
Datasheets

Specifications of 78P2351-IGTR/F

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Design Guidelines for TERIDIAN 78P235x LIUs
ANALOG SIGNAL TRACES AND TERMINATIONS
The 78P235x LIUs have differential drivers and receivers. To maintain signal integrity and optimal performance,
all differential traces should be of equal length, parallel to each other, and as short as possible. The impedance of
such traces and terminations should also be well controlled.
For the Reset pin (PORB), do not tie directly to VCC as this will prevent internal power-on reset. Connect to a
microcontroller for manual reset or de-couple to ground using a 1nF capacitor.
Each LVPECL interface should have a differential trace impedance of 100Ω to the SerDes. For best return loss,
the input termination resistors should be placed within one inch of their 78P235x input pins. LVPECL output
drivers require an external pull-down resistor, which should also be placed near the output pin. See Figure 2 and
Figure 3 for diagrams of recommended terminations of LVPECL I/Os.
Page 3 of 15
transmitting
NOTES
1. For DC-coupling, the common mode or bias voltage levels of both ICs must be compatible. Reference product
2.
from
chip
specifications for more information on bias levels or AC-couple.
For E4 applications, DC coupling is required due to the unframed nature of AIS (all ones) signaling in E4.
:
50 ohm
50 ohm
from circuit
from circuit
Figure 3: LVPECL Inputs (DC-coupled and 0.1uF AC-coupled options)
100
PCB
< 1"
< 1"
VCC
VCC
LVPECL Output (PO)
LVPECL Input (PI)
235x IC
Reff
20
20
235x IC
 2008 Teridian Semiconductor Corp.
Figure 2: LVPECL Outputs
PCB
to gates
to gates
170
170
transmitting
50 ohm
from
chip
50 ohm
< 20"
50 ohm
50 ohm
< 1"
< 1"
to LVPECL
input
170
82
PCB
3.3V
170
82
235x IC
Rev 2.1

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