78P2351-IGTR/F Maxim Integrated Products, 78P2351-IGTR/F Datasheet - Page 10

• Manufacturer Part Number: 78P2351-IGTR/F
• Description: LINE INTERFACE UNIT 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of 78P2351-IGTR/F

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Design Guidelines for TERIDIAN 78P235x LIUs
PCB GUIDELINES FOR THERMALLY ENHANNCED 128-PIN LQFPS
metal pad or exposed heat slug on the package, as shown in Figure 9. The size of this land pattern can be larger,
smaller, or even take on a different shape than the exposed pad on the package. However, the solderable area,
as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the
package to maximize the thermal performance. A clearance of at least 0.25mm should be designed on the PWB
between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PWB provides a means of heat transfer from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from the surface of the PWB to the ground plane(s).
These vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific and dependent upon
the package power dissipation as well as electrical conductivity requirements. Thus, thermal analysis and/or
testing are recommended to determine the minimum number needed. Maximum thermal performance is
achieved when an array of vias is incorporated in the land pattern at 1.2mm grid, as shown in Figure 10. It is
also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1 oz copper via barrel
plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result
in voids in solder between the exposed pad/slug and the thermal land. If the copper plating does not plug the vias,
the thermal vias can be “tented” with solder mask on the top surface of the PWB to avoid solder wicking inside the
via during assembly. The solder mask diameter should be at least 4mils (0.1mm) larger than the diameter of the
via.
Stencil Design
For maximum thermal performance, it is required that the exposed pad/slug on the package be soldered to the
land pattern on the PWB. This can be achieved by applying solder paste on both the pattern for lead attachment
as well as on the land pattern for the exposed pad. While for standard (non-thermally enhanced) leadframe based
packages the stencil thickness depends on the lead pitch and package coplanarity, the package standoff must
also be considered for the thermally enhanced packages to determine the stencil thickness. For a nominal
standoff of 0.1mm, the stencil thickness of 5 to 8mils (depending upon the pitch) is recommended. The aperture
openings should be the same as the solder mask opening on the land pattern (i.e. 1:1). Since a large stencil
opening may result in poor release, the aperture opening should be subdivided into an array of smaller openings,
similar to the thermal land pattern shown in Figure 11. The above guidelines will result in the solder joint area to
be about 80 to 90% of the exposed pad/slug area.
Page 10 of 15
0.25mm
Figure 9: Land Pattern
Thermally enhanced or exposed pad LQFPs have an exposed paddle or solder slug on the
bottom of the package to provide the primary heat removal path. Although the land pattern
design for lead attachment on the PCB should be the same as that for conventional, non-
thermally enhanced packages, extra features are required during the PCB design and
assembly stage for effectively mounting thermally enhanced packages.
In order to maximize both the removal of heat from the package, a land pattern must be
incorporated on the PWB within the footprint of the package corresponding to the exposed
Solder Mask
Opening
Thermal
Land
 2008 Teridian Semiconductor Corp.
Figure 10: Via Grid
0.3mm
1.2mm
Figure 11: PCB Stencil Design
(78P2352 ONLY)
1x1 Sq. mm
1.2mm
Rev 2.1