MCIMX31LCVMN4C Freescale Semiconductor, MCIMX31LCVMN4C Datasheet - Page 58

IC MPU MAP I.MX31L 473-MAPBGA

MCIMX31LCVMN4C

Manufacturer Part Number
MCIMX31LCVMN4C
Description
IC MPU MAP I.MX31L 473-MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX31r
Datasheets

Specifications of MCIMX31LCVMN4C

Core Processor
ARM11
Core Size
32-Bit
Speed
400MHz
Connectivity
1-Wire, ATA, EBI/EMI, FIR, I²C, MMC/SD, PCMCIA, SIM, SPI, SSI, UART/USART, USB, USB OTG
Peripherals
DMA, LCD, POR, PWM, WDT
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.22 V ~ 3.3 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
473-MAPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCIMX31LCVMN4C
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCIMX31LCVMN4CR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
3
where CEIL(X) rounds the elements of X to the nearest integers towards infinity.
Electrical Characteristics
4.3.15.3 Interface to Sharp HR-TFT Panels
Figure 49
CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY,
REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and
SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to
Section 4.3.15.2.2, “Interface to Active Matrix TFT LCD Panels, Electrical Characteristics,” on page 55.
The timing images correspond to straight polarity of the Sharp signals.
58
Tdicu
Display interface clock up time
DISPB_D3_DATA
DISPB_D3_SPL
DISPB_D3_CLS
DISPB_D3_REV
=
DISPB_D3_PS
DISPB_D3_CLK
DISPB_D3_HSYNC
1
-- - T
2
depicts the Sharp HR-TFT panel interface timing, and
HSP_CLK
Figure 49. Sharp HR-TFT Panel Interface Timing Diagram—Pixel Level
ceil
2 DISP3_IF_CLK_UP_WR
--------------------------------------------------------------------- -
HSP_CLK_PERIOD
SPL pulse width is fixed and aligned to the first data of the line.
Example is drawn with FW+1=320 pixel/line, FH+1=240 lines.
REV toggles every HSYNC period.
IP24
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
IP22
Horizontal timing
IP21
IP23
IP25
D1 D2
IP26
1 DISPB_D3_CLK period
Table 46
D320
lists the timing parameters. The
Freescale Semiconductor

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