MCF5328CVM240 Freescale Semiconductor, MCF5328CVM240 Datasheet - Page 23

• Manufacturer Part Number: MCF5328CVM240
• Description: IC MCU 32BIT 240MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF532xr

Specifications of MCF5328CVM240

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSI, UART/USART, USB, USB OTG
• Peripherals: DMA, LCD, PWM, WDT
• Number Of I /o: 94
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Program Memory Size: 16KB
• Cpu Speed: 240MHz
• Embedded Interface Type: CAN, I2C, MAC, Ethernet, QSPI, UART
• Rohs Compliant: Yes
• Family Name: MPC5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 240MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.6/1.95/2.75/3.6V
• Operating Supply Voltage (min): 1.4/1.7/2.25/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

5.7
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports standard SDRAM or
double data rate (DDR) SDRAM, but it does not support both at the same time.
5.7.1
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the memory bus clock,
when operating in SDR mode on write cycles and relative to SD_DQS on read cycles. The device’s SDRAM controller is a
DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must remain supplied to the device
for each data beat of an SDR read. The processor accomplishes this by asserting a signal named SD_SDR_DQS during read
cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the
SD_SDR_DQS signal and its usage.
Freescale Semiconductor
Symbol
SD1
SD3
SD4
SD5
SD6
SD7
SD8
•
Frequency of Operation
Clock Period
Pulse Width High
Pulse Width Low
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Valid
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Hold
SD_SDR_DQS Output Valid
SD_DQS[3:0] input setup relative to SD_CLK
SDRAM Bus
SDR SDRAM AC Timing Characteristics
FB_CSn, FB_BE/BWEn
2
4
3
FB_D[31:X]
Characteristic
MCF532x ColdFire
1
FB_A[23:0]
FB_CLK
FB_R/W
5
FB_OE
FB_TS
FB_TA
Table 10. SDR Timing Specifications
Figure 8. FlexBus Write Timing
FB1
ADDR[31:X]
®
S0
FB2
6
Microprocessor Data Sheet, Rev. 5
FB6
ADDR[23:0]
S1
t
DATA
t
t
DQVSDCH
Symbol
SDCHACV
SDCHACI
t
t
t
t
SDCKH
SDCKH
DQSOV
SDCK
S2
•
FB7
SD_CLK
0.25 ×
12.5
0.45
0.45
Min
2.0
60
—
—
S3
FB3
0.40 × SD_CLK
0.5 × SD_CLK
Electrical Characteristics
Self timed
16.67
+ 1.0
Max
0.55
0.55
80
—
SD_CLK
SD_CLK
Unit
MHz
ns
ns
ns
ns
ns
23