AT91SAM7S128C-AU Atmel, AT91SAM7S128C-AU Datasheet - Page 166

IC ARM7 MCU 32BIT 128K 64LQFP

AT91SAM7S128C-AU

Manufacturer Part Number
AT91SAM7S128C-AU
Description
IC ARM7 MCU 32BIT 128K 64LQFP
Manufacturer
Atmel
Series
AT91SAMr

Specifications of AT91SAM7S128C-AU

Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
AT91SAM7S128-AU-001
AT91SAM7S128AU001
AT91SAM7S128AU001

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7S128C-AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT91SAM7S128C-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
AT91SAM7S128C-AU-999
Manufacturer:
Atmel
Quantity:
10 000
23.7.2
23.7.2.1
166
AT91SAM7S Series Preliminary
Interrupt Latencies
External Interrupt Edge Triggered Source
Global interrupt latencies depend on several parameters, including:
This section addresses only the hardware resynchronizations. It gives details of the latency
times between the event on an external interrupt leading in a valid interrupt (edge or level) or the
assertion of an internal interrupt source and the assertion of the nIRQ or nFIQ line on the pro-
cessor. The resynchronization time depends on the programming of the interrupt source and on
its type (internal or external). For the standard interrupt, resynchronization times are given
assuming there is no higher priority in progress.
The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt
sources.
Figure 23-6.
• The time the software masks the interrupts.
• Occurrence, either at the processor level or at the AIC level.
• The execution time of the instruction in progress when the interrupt occurs.
• The treatment of higher priority interrupts and the resynchronization of the hardware signals.
External Interrupt Edge Triggered Source
(Negative Edge)
(Positive Edge)
IRQ or FIQ
IRQ or FIQ
nIRQ
MCK
nFIQ
Maximum IRQ Latency = 4 Cycles
Maximum FIQ Latency = 4 Cycles
6175K–ATARM–30-Aug-10

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