TFF1003HN/N1,115 NXP Semiconductors, TFF1003HN/N1,115 Datasheet - Page 7

• Manufacturer Part Number: TFF1003HN/N1,115
• Description: IC FREQUENCY GEN TX/TXRX 24HVQFN
• Manufacturer: NXP Semiconductors
• Type: Ku Frequency Generatorr

Specifications of TFF1003HN/N1,115

• Package / Case: 24-VFQFN Exposed Pad
• Mounting Type: Surface Mount
• Voltage - Supply: 3 V ~ 3.6 V
• Frequency-max: 13.05GHz
• Operating Temperature: -40°C ~ 85°C
• Output: Clock
• Input: Clock
• Maximum Input Frequency: 816 MHz
• Minimum Input Frequency: 50 MHz
• Output Frequency Range: 12.8 GHz to 13.05 GHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Input Level: - 10 dBm
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Output Level: - 5 dBm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
TFF1003HN_1
Product data sheet
Fig 6.
actual PLL status
timeline section
IN(REF)_P/N(t)
(1) The attack time and decay time are typically 10 μs and are mainly depending on the drift of the VCO tuning voltage.
LCKDET(t)
upper window detector threshold
VTUNE(t)
low window detector threshold
remarks
VTUNE
Timing diagram lock detector
(93% of V O(reg)VCO )
OUT OF LOCK (0 V)
(7% of V O(reg)VCO )
10.4 Reference input (IN(REF)_P, IN(REF)_N)
IN LOCK
Table 6.
LCKDET (pin 7) has a pull-down resistor of 100 kΩ to GND1(REF) (pin 8).
The reference input is a differential pair and is internally biased. The input is high ohmic.
The input signal must be AC coupled. If used in a single ended mode, the not used input
must be terminated with the same impedance as the driving source.
An example of the differential source and two single ended loads are shown in
An example of a single ended application is shown in
Logical value
0
1
2.2 V
0.4 V
value determined
LCKDET > 2.2 V
opertation PLL
by closed loop
PLL is in lock
hysteresis voltage (0.1 V)
hysteresis voltage (0.1 V)
Logical value and physical value for lock detect (LCKDET)
1
All information provided in this document is subject to legal disclaimers.
PLL is out of lock PLL is out of lock PLL is out of lock
Drift to maximum
voltage = lowest
remains > 2.2 V
because loop
frequency of
filter is still
LCKDET
charged
VCO
Rev. 01 — 19 May 2010
2
Physical value
0 V
2.5 V
LCKDET changes
< 0.4 V during the
behavior around
window detector
window detector
VTUNE > upper
from > 2.2 V to
Low phase noise LO generator for VSAT applications
undetermined
attack time
detects that
attack time
threshold.
maximum
voltage
3
(1)
LCKDET < 0.4 V
behavior around
undetermined
maximum
voltage
4
Figure
LCKDET changes
> 2.2 V during the
threshold − 0.1 V.
by loop to closed
voltage is forced
window detector
window detector
VTUNE < upper
from < 0.4 V to
PLL is in lock
decay time
loop value of
detects that
decay time
PLL
Lock detect state
out of lock
lock
8.
5
(1)
TFF1003HN
© NXP B.V. 2010. All rights reserved.
value is determined by
closed loop operation
LCKDET > 2.2 V
PLL is in lock
6
PLL
Figure
001aal986
t
t
t
7 of 17
7.