TFF1003HN/N1,115 NXP Semiconductors, TFF1003HN/N1,115 Datasheet - Page 6

• Manufacturer Part Number: TFF1003HN/N1,115
• Description: IC FREQUENCY GEN TX/TXRX 24HVQFN
• Manufacturer: NXP Semiconductors
• Type: Ku Frequency Generatorr

Specifications of TFF1003HN/N1,115

• Package / Case: 24-VFQFN Exposed Pad
• Mounting Type: Surface Mount
• Voltage - Supply: 3 V ~ 3.6 V
• Frequency-max: 13.05GHz
• Operating Temperature: -40°C ~ 85°C
• Output: Clock
• Input: Clock
• Maximum Input Frequency: 816 MHz
• Minimum Input Frequency: 50 MHz
• Output Frequency Range: 12.8 GHz to 13.05 GHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Input Level: - 10 dBm
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Output Level: - 5 dBm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
TFF1003HN_1
Product data sheet
Fig 4.
Type 2 loop filter
VTUNE
3
10.2 Output buffer
10.3 Lock detector
30 pF
C1
Table 5.
The output consists of a differential pair with 50 Ω collector resistors R
only one output is used, terminate the non used output with the same impedance as the
load (see
The lock detector is the output of a window detector. The window detector compares the
output voltage over the charge pump. This voltage is identical to VTUNE when a
type 2 loop filter is used (see
by R2/C3 (see
The lower window detector threshold voltage is 7 % of the output voltage on
VREGVCO (pin 1), the upper window detector threshold voltage is 93 % of the output
voltage on VREGVCO (pin 1). The hysteresis is 0.1 V. The output is 2.5 V CMOS
compliant. The values are shown in
At start-up the LCKDET (pin 7) will be LOW until the circuit has acquired lock.
f
(MHz)
50.000 to 50.977
100.000 to 101.953
200.000 to 203.906
400.000 to 407.813
800.000 to 815.625
C2
i(ref)
CPOUT
2
10 pF
R1
Figure
Component values used for characterization
VREGVCO
1
2.7 V
Figure
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8)
5). Due to this filtering the attack and decay time will decrease.
Rev. 01 — 19 May 2010
Figure
Divider value
256
128
64
32
16
Low phase noise LO generator for VSAT applications
Fig 5.
Table
4). In case of a type 3 loop filter this voltage is filtered
6. The timing diagram is shown in
Type 3 loop filter
VTUNE
3
R2
30 pF
C1
(nF)
27
18
18
33
68
C1
C3
C2
CPOUT
2
C2
(pF)
82
82
120
270
560
10 pF
R1
TFF1003HN
C3
(pF)
33
33
33
33
33
BUF_P
VREGVCO
1
2.7 V
© NXP B.V. 2010. All rights reserved.
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and R
R1
(Ω)
470
330
270
120
68
Figure
BUF_N
R2
(Ω)
560
560
560
560
560
6.
6 of 17
. If