X5323S8IZ Intersil, X5323S8IZ Datasheet - Page 7

• Manufacturer Part Number: X5323S8IZ
• Description: IC CPU SUPERV 32K EE 8-SOIC
• Manufacturer: Intersil
• Type: Simple Reset/Power-On Resetr

Specifications of X5323S8IZ

• Number Of Voltages Monitored: 1
• Output: Open Drain or Open Collector
• Reset: Active Low
• Reset Timeout: 100 ms Minimum
• Voltage - Threshold: 4.38V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI Serial Memory
The memory portion of the device is a CMOS serial EEPROM
array with Intersil’s block lock protection. The array is
internally organized as x8. The device features a Serial
Peripheral Interface (SPI) and software protocol allowing
operation on a simple four-wire bus.
The device utilizes Intersil’s proprietary Direct Write
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input, with
data being clocked in on the rising edge of SCK. CS must be
LOW during the entire operation.
All instructions (Table 1), addresses and data are transferred
MSB first. Data input on the SI line is latched on the first
rising edge of SCK after CS goes LOW. Data is output on the
SO line by the falling edge of SCK. SCK is static, allowing
the user to stop the clock and then start it again to resume
operations where left off.
Write Enable Latch
The device contains a write enable latch. This latch must be
SET before a write operation is initiated. The WREN
instruction will set the latch and the WRDI instruction will
reset the latch (Figure 3). This latch is automatically reset
upon a power-up condition and after the completion of a
valid write cycle.
NOTE: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
INSTRUCTION NAME
WREN CMD
WRDI/RFLB
WEL
0
1
1
1
WRITE
WREN
WRSR
RSDR
READ
SFLB
STATUS REGISTER
WPEN
INSTRUCTION FORMAT*
X
1
0
X
7
0000 0000
0000 0100
0000 0101
0000 0001
0000 0010
0000 0110
0000 0011
DEVICE PIN
WP
X
0
X
1
TABLE 2. BLOCK PROTECT MATRIX
TABLE 1. INSTRUCTION SET
™
Set the write enable latch (enable write operations)
Set flag bit
Reset the write enable latch/reset flag bit
Read status register
Write status register (watchdog, block lock, WPEN and flag bits)
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
cell,
X5323, X5325
Protected Block
Protected
Protected
Protected
Protected
BLOCK
Status Register
The RDSR instruction provides access to the status register.
The status register may be read at any time, even during a
write cycle. The status register is formatted as follows:
The Write-In-Progress (WIP) bit is a volatile, read only bit
and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.
The Write Enable Latch (WEL) bit indicates the status of
the write enable latch. When WEL = 1, the latch is set
HIGH and when WEL = 0 the latch is reset LOW. The WEL
bit is a volatile, read only bit. It can be set by the WREN
instruction and can be reset by the WRDS instruction.
The block lock bits, BL0 and BL1, set the level of block lock
protection. These nonvolatile bits are programmed using the
WRSR instruction and allow the user to protect one quarter,
one half, all or none of the EEPROM array. Any portion of the
array that is block lock protected can be read but not written. It
will remain protected until the BL bits are altered to disable
block lock protection of that portion of memory.
WPEN
7
Unprotected Block
FLB
6
Protected
OPERATION
Writable
Writable
BLOCK
Writable
WD1
5
WD0
4
WPEN, BL0, BL1 WD0, WD1
BL1
3
STATUS REGISTER
BL0
Protected
Protected
Writable
Writable
2
WEL
1
June 30, 2008
FN8131.2
WIP
0