X5323S8IZ Intersil, X5323S8IZ Datasheet
X5323S8IZ
Specifications of X5323S8IZ
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X5323S8IZ Summary of contents
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... All other trademarks mentioned are the property of their respective owners. X5323, X5325 (Replaces X25323, X25325) FN8131.2 detection and reset assertion reset threshold voltage using protection RESET/RESET X5323 = RESET X5325 = RESET RESET | Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved ...
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... X5323PI X5323P I X5325PI X5323PIZ (Note) X5323P ZI X5325PIZ X5323S8* X5323 X5325S8* X5323S8Z* (Note) X5323 Z X5325S8Z* (Note) X5323S8I* X5323 I X5325S8I* X5323S8IZ* (Note) X5323 ZI X5325S8IZ* (Note) X5323V14* X5323 V X5325V14* X5323V14Z* (Note) X5323 VZ X5325V14Z* (Note) X5323V14I* X5323 VI X5325V14I* X5323V14IZ* (Note) X5323 VZI X5325V14IZ* (Note) X5323P-2.7A X5323P AN X5325P-2 ...
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... X5325PZ-2.7 X5323PI-2.7 X5323P G X5325PI-2.7 X5323PIZ-2.7 (Note) X5323P ZG X5325PIZ-2.7 X5323S8-2.7* X5323 F X5325S8-2.7* X5323S8Z-2.7* (Note) X5323 ZF X5325S8Z-2.7* (Note) X5325 ZF X5323S8I-2.7* X5323 G X5325S8I-2.7* X5323S8IZ-2.7* (Note) X5323 ZG X5325S8IZ-2.7* (Note) X5325 ZG X5323V14-2.7* X5323 VF X5325V14-2.7* X5323V14Z-2.7* X5323 VZF X5325V14Z-2.7* (Note) (Note) X5323V14I-2.7* X5323 VG X5325V14I-2.7* X5323V14IZ-2.7* X5323 VZG X5325V14IZ-2 ...
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Pin Descriptions PIN NUMBER PIN NUMBER (SOIC/PDIP) TSSOP PIN NAME 1 1 CS/WDI SCK RESET/ RESET ...
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Principles of Operation Power-on Reset Application of power to the X5323/X5325 activates a power-on reset circuit. This circuit goes active at about 1V and pulls the RESET/RESET pin active. This signal prevents the system microprocessor from starting to operate with ...
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NEW V APPLIED = CC OLD V APPLIED + ERROR CC ERROR ≤ EMAX EMAX = MAXIMUM DESIRED ERROR FIGURE 3. V 4.7kΩ V TRIP ADJ. + PROGRAM 6 X5323, X5325 V PROGRAMMING TRIP EXECUTE RESET V TRIP SEQUENCE SET ...
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... SPI Serial Memory The memory portion of the device is a CMOS serial EEPROM array with Intersil’s block lock protection. The array is internally organized as x8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Intersil’s proprietary Direct Write providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years ...
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STATUS REGISTER BITS ARRAY ADDRESSES PROTECTED BL1 BL0 X5323/X5325 0 0 None (factory default $0C00 to $0FFF 1 0 $0800 to $0FFF 1 1 $0000 to $0FFF The watchdog timer bits, WD0 and WD1, select the watchdog ...
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When the highest address is reached, the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS high. Refer to the read EEPROM Array Sequence (Figure 1). ...
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SCK SI HIGH IMPEDANCE SO FIGURE 7. WRITE ENABLE LATCH SEQUENCE SCK INSTRUCTION SCK DATA BYTE ...
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... This parameter is periodically sampled and not 100% tested. 11 X5323, X5325 Thermal Information Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. SYMBOL ...
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Equivalent AC Load Circuit 2.06kΩ OUTPUT RESET/RESET 3.03kΩ 100pF AC Electrical Specifications Input pulse levels = V level = V PARAMETER SERIAL INPUT TIMING Clock Frequency Cycle Time CS Lead Time CS Lag Time Clock HIGH ...
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Serial Output Timing PARAMETER Clock Frequency Output Disable Time Output Valid From Clock Low Output Hold Time Output Rise Time Output Fall Time NOTES: 3. This parameter is periodically sampled and not 100% tested the time from ...
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RESET Output Timing SYMBOL V Reset Trip Point Voltage, X5323-4.5A, X5323-4.5A TRIP Reset Trip Point Voltage, X5323, X5325 Reset Trip Point Voltage, X5323-2.7A, X5325-2.7A Reset Trip Point Voltage, X5323-2.7, X5325-2 Hysteresis (HIGH to LOW vs LOW to HIGH ...
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V Set Conditions TRIP TRIP SCK Reset Conditions TRIP SCK > PROGRAMMED V CC TRIP V Programming Specifications TRIP PARAMETER ...
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V Programming Specifications TRIP PARAMETER t V Write Cycle Time WC TRIP t V Program Cycle Recovery Period (Between Successive Programming Cycles) RP TRIP t SCK V Program Voltage Off-Time Before Next Cycle VPO TRIP V Programming Voltage P V ...
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Typical Performance Curves 205 200 195 190 185 180 175 170 165 160 -40 25 TEMPERATURE (°C) FIGURE 14 TEMPERATURE PURST 17 X5323, X5325 205 200 195 +25°C 190 +90°C 185 180 175 170 165 160 90 1.7 ...
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Plastic Dual-In-Line Packages (PDIP) D SEATING PLANE MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL PDIP8 PDIP14 A 0.210 0.210 A1 0.015 0.015 A2 0.130 0.130 b 0.018 0.018 b2 0.060 0.060 c 0.010 0.010 D 0.375 0.750 E 0.310 ...
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Small Outline Package Family (SO PIN #1 I.D. MARK 0.010 SEATING PLANE 0.004 C 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...