X5325 Intersil Corporation, X5325 Datasheet
X5325
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X5325 Summary of contents
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... CC falls below the minimum V CC returns to CC thresholds are available, however, Intersil’s RESET/RESET X5323 = RESET X5325 = RESET Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved the trip CC ...
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... PART NUMBER RESET PART (ACTIVE LOW) MARKING X5323P-4.5A X5323P AL X5325P-4.5A X5323PZ-4.5A (Note) X5323P Z AL X5325PZ-4.5A X5323PI-4.5A X5323P AM X5325PI-4.5A X5323PIZ-4.5A (Note) X5323P Z AM X5325PIZ-4.5A X5323S8-4.5A X5323 AL X5325S8-4.5A X5323S8Z-4.5A (Note) X5323 Z AL X5325S8Z-4.5A (Note) X5325 Z AL X5323S8I-4.5A* X5323 AM X5325S8I-4.5A X5323S8IZ-4.5A* X5323 Z AM X5325S8IZ-4.5A (Note) (Note) X5323V14-4 ...
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... X5323PIZ-2.7 (Note) X5323P Z G X5325PIZ-2.7 X5323S8-2.7* X5323 F X5325S8-2.7* X5323S8Z-2.7* (Note) X5323 Z F X5325S8Z-2.7* (Note) X5325 Z F X5323S8I-2.7* X5323 G X5325S8I-2.7* X5323S8IZ-2.7* (Note) X5323 Z G X5325S8IZ-2.7* (Note) X5325 Z G X5323V14-2.7* X5325V14-2.7* X5323V14Z-2.7* X5323V Z F X5325V14Z-2.7* (Note) (Note) X5323V14I-2.7* X5325V14I-2.7* X5323V14IZ-2.7* X5323V Z G X5325V14IZ-2.7* ...
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... SCK RESET/ RESET 3-5,10- X5323, X5325 CS/WDT RESET/RESET NC 6 SCK Chip Select Input. CS HIGH, deselects the device and the SO output pin high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode ...
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... PRINCIPLES OF OPERATION Power-on Reset Application of power to the X5323/X5325 activates a power-on reset circuit. This circuit goes active at about 1V and pulls the RESET/RESET pin active. This signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. As long as RESET/RESET pin is active, the device will not respond to any Read/Write instruction ...
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... Figure 3. V Programming Sequence Flow Chart TRIP New V Applied = CC Old V Applied + Error CC Emax = Maximum Desired Error Figure 4. Sample V Reset Circuit TRIP 4.7K V TRIP Adj. Program 6 X5323, X5325 V Programming TRIP Execute Reset V TRIP Sequence Set Applied = CC CC Desired V TRIP Execute Set V TRIP Sequence ...
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... X 7 X5323, X5325 Write Enable Latch The device contains a write enable latch. This latch must be SET before a write operation is initiated. The WREN instruction will set the latch and the WRDI instruction will reset the latch (Figure 3). This latch is automatically reset upon a power-up condition and after the completion of a valid write cycle. ™ ...
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... SCK Instruction SI High Impedance SO 8 X5323, X5325 The watchdog timer bits, WD0 and WD1, select the watchdog time out period. These nonvolatile bits are programmed with the WRSR instruction. Status Register Bits WD1 The FLAG bit shows the status of a volatile latch that can be set and reset by the system using the SFLB and RFLB instructions ...
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... After the RDSR opcode is sent, the contents of the status register are shifted out on the SO line. Refer to the read status register sequence (Figure 2). 9 X5323, X5325 Write Sequence Prior to any attempt to write data into the device, the “Write Enable” Latch (WEL) must first be set by issuing the WREN instruction (Figure 3) ...
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... Figure 7. Write Enable Latch Sequence CS SCK SI SO Figure 8. Write Sequence SCK Instruction SCK Data Byte X5323, X5325 Instruction MSB High Impedance 4 ...
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... LOW to HIGH to HIGH May change Will change from HIGH from HIGH to LOW to LOW Don’t Care: Changing: Changes State Not Allowed Known N/A Center Line is High Impedance 11 X5323, X5325 Instruction Data Byte FN8131 ...
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... IL IH (2) This parameter is periodically sampled and not 100% tested. 12 X5323, X5325 COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. .... -1.0V to +7V This is a stress rating only; the functional operation of the ...
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... Data hold time H (3) t Input rise time RI (3) t Input fall time deselect time CS (4) t Write cycle time WC 13 X5323, X5325 A.C. TEST CONDITIONS CC Input pulse levels 5V Input rise and fall times Input and output timing level 4.6kΩ 30pF Parameter 10ns V x0.5 CC 2.7– ...
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... CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile WC write cycle. Serial Output Timing CS SCK MSB Out ADDR SI LSB IN 14 X5323, X5325 Parameter t t CYC MSB–1 Out t ...
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... RESET Output Timing Symbol V Reset trip point voltage, X5323-4.5A, X5323-4.5A TRIP Reset trip point voltage, X5323, X5325 Reset trip point voltage, X5323-2.7A, X5325-2.7A Reset trip point voltage, X5323-2.7, X5325-2 hysteresis (HIGH to LOW vs. LOW to HIGH V TH TRIP t Power-up reset time out ...
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... Set Conditions TRIP TRIP SCK Reset Conditions TRIP SCK > Programmed V CC TRIP 16 X5323, X5325 Min. 100 450 1 400 100 t THD t TSU VPH VPS VPO VPH VPS t VPO ...
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... TRIP at 25° program variation after programming (0–75°C). (programmed at 25°C) tv TRIP V programming parameters are periodically sampled and are not 100% tested. TRIP 17 X5323, X5325 = 1.7–5.5V; Temperature = 0°C to 70°C CC Description applied-V ) (programmed at 25°C) CC TRIP applied-V CC Min. Max. ...
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... Temperature t vs. Temperature PURST 205 200 195 190 185 180 175 170 165 160 -40 25 Degrees °C 18 X5323, X5325 ) t vs. Voltage/Temperature (WD1 WDO 1.9 = 5V) 1.8 CC 1.7 1.6 = 5V) 1.5 CC 1.4 1.3 1.2 1.1 = 3V, 5V vs. Voltage/Temperature (WD1 WDO TRIP 0 ...
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... PACKAGING INFORMATION 8-Lead Plastic Small Outline Gull Wing Package Type S Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0° - 8° 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 19 X5323, X5325 Pin 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.050 (1.27) X 45° 0.0075 (0.19) 0.250" 0.010 (0.25) FOOTPRINT 0 ...
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... PACKAGING INFORMATION Half Shoulder Width On All End Pins Optional .073 (1.84) Typ. 0.010 (0.25) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 20 X5323, X5325 8-Lead Plastic Dual In-Line Package Type P 0.430 (10.92) 0.360 (9.14) Pin 1 Index Pin 1 0.300 (7.62) Ref. Seating Plane 0.150 (3.81) ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 21 X5323, X5325 14-Lead Plastic, TSSOP, Package Type V .025 (.65) BSC .169 (4.3) ...