AD600JNZ Analog Devices Inc, AD600JNZ Datasheet - Page 6

• Manufacturer Part Number: AD600JNZ
• Description: IC AMP VGA DUAL LN 50MA 16DIP
• Manufacturer: Analog Devices Inc
• Series: X-AMP®r

Specifications of AD600JNZ

• Amplifier Type: Variable Gain
• Number Of Circuits: 2
• Slew Rate: 275 V/µs
• -3db Bandwidth: 35MHz
• Current - Input Bias: 350nA
• Current - Supply: 11mA
• Current - Output / Channel: 50mA
• Voltage - Supply, Single/dual (±): ±4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• No. Of Amplifiers: 1
• Bandwidth: 35MHz
• Gain Accuracy: 1dB
• No. Of Channels: 1
• Supply Voltage Range: ± 4.75V To ± 5.25V
• Amplifier Case Style: DIP
• No. Of Pins: 16
• Operating Temperature Range: 0°C To
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• Gain Bandwidth Product: -
• Voltage - Input Offset: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD600/AD602
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
C1LO
A1HI
A1LO
GAT1
GAT2
A2LO
A2HI
C2LO
C2HI
A2CM
A2OP
VNEG
VPOS
A1OP
A1CM
C1HI
Description
CH1 Gain-Control Input LO (Positive Voltage Reduces CH1 Gain)
CH1 Signal Input HI (Positive Voltage Increases CH1 Output)
CH1 Signal Input LO (Usually Connected to CH1 Input Ground)
CH1 Gating Input (A Logic HI Shuts Off CH1 Signal Path)
CH2 Gating Input (A Logic HI Shuts Off CH2 Signal Path)
CH2 Signal Input LO (Usually Connected to CH2 Input Ground)
CH2 Signal Input HI (Positive Voltage Increases CH2 Output)
CH2 Gain-Control Input LO (Positive Voltage Reduces CH2 Gain)
CH2 Gain-Control Input HI (Positive Voltage Increases CH2 Gain)
CH2 Common (Usually Connected to CH2 Output Ground)
CH2 Output
Negative Supply for Both Amplifiers
Positive Supply for Both Amplifiers
CH1 Output
CH1 Common (Usually Connected to CH1 Output Ground)
CH1 Gain-Control Input HI (Positive Voltage Increases CH1 Gain)
C1LO
A1LO
A2LO
C2LO
GAT1
GAT2
A1HI
A2HI
Figure 2. Pin Configuration
1
2
3
4
5
6
7
8
Rev. E | Page 6 of 28
+
–
–
+
AD600 /
AD602
A1
A2
REF
16
15
14
13
12
11
10
9
C1HI
A1CM
A1OP
VPOS
VNEG
A2OP
A2CM
C2HI