SAK-C161JC-LF CA Infineon Technologies, SAK-C161JC-LF CA Datasheet
SAK-C161JC-LF CA
Specifications of SAK-C161JC-LF CA
SP000057699
Related parts for SAK-C161JC-LF CA
SAK-C161JC-LF CA Summary of contents
Page 1
...
Page 2
... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
Page 3
...
Page 4
C161CS/JC/JI Revision History: Previous Version: Page Subjects (major changes since last revision) All Converted to Infineon layout 2 Derivative Synopsis Table updated 4, 6, 10, 18 Programmable Interface Routing introduced 27, 28 GPT block diagrams updated 29 RTC description improved ...
Page 5
Single-Chip Microcontroller C166 Family C161CS/JC/JI • High Performance 16-bit CPU with 4-Stage Pipeline – Instruction Cycle Time at 25 MHz CPU Clock – 400 ns Multiplication (16 – Enhanced Boolean Bit Manipulation Facilities – Additional Instructions to ...
Page 6
... Table 1 C161CS/JC/JI Derivative Synopsis Derivative SAK-C161CS-32RF SAB-C161CS-32RF SAK-C161CS-LF SAB-C161CS-LF SAK-C161JC-32RF SAB-C161JC-32RF SAK-C161JC-LF SAB-C161JC-LF SAK-C161JI-32RF SAB-C161JI-32RF SAK-C161JI-LF SAB-C161JI-LF For simplicity all versions are referred to by the term C161CS/JC/JI throughout this document. Data Sheet On-Chip Serial Bus Program Memory Interface(s) 256 KByte ROM ...
Page 7
Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: • the derivative itself, i.e. its function set, the temperature range, and the supply voltage • the package and the ...
Page 8
Pin Configuration (top view) RSTOUT 1 NMI P6.0/CS0 5 P6.1/CS1 6 P6.2/CS2 7 P6.3/CS3 8 P6.4/CS4 9 P6.5/HOLD 10 P6.6/HLDA 11 P6.7/BREQ 12 P7.4/CC28IO/* 13 P7.5/CC29IO/* 14 P7.6/CC30IO/* 15 P7.7/CC31IO ...
Page 9
Table 2 Pin Definitions and Functions Symbol Pin Input No. Outp. RST 1 O OUT NMI P6.6 11 ...
Page 10
Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input No. Outp P7 P7 P7 P7 ...
Page 11
Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input No. Outp P5.12 37 ...
Page 12
Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input No. Outp P2.8 43 I/O I P2.9 44 I/O I P2.10 45 I/O I P2.11 46 I/O I P2.12 47 I/O I P2.13 48 I/O I P2.14 49 ...
Page 13
Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input No. Outp P3 P3 I ...
Page 14
Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input No. Outp ...
Page 15
Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input No. Outp. READY 82 I ALE PORT0 IO P0L.0-7 85- 92 P0H.0-7 95- 102 Data Sheet Function Ready Input. When the Ready function is enabled, ...
Page 16
Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input No. Outp. PORT1 IO P1L.0-7 103- 110 P1H.0-7 113- 120 P1H.4 117 I/O P1H.5 118 I/O P1H.6 119 I/O P1H.7 120 I/O XTAL2 123 O XTAL1 124 I XTAL3 126 ...
Page 17
Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input No. Outp. RSTIN 128 I – AREF V 36 – AGND V 4, 18, – 42, 52, 68, 78, 93, 111, 121 V 3, ...
Page 18
Note: The following behavioural differences must be observed when the bidirectional reset is active: • Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared automatically after a reset. • The reset indication flags always indicate a ...
Page 19
Functional Description The architecture of the C161CS/JC/JI combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the on-chip memory blocks allow the design of compact systems with maximum performance. ...
Page 20
Memory Organization The memory space of the C161CS/JC/JI is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire ...
Page 21
External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required one of four different ...
Page 22
Note: When one or both of the on-chip CAN Modules or the SDLM are used with the interface lines assigned to Port 4, the interface lines override the segment address lines and the segment address output on Port 4 is ...
Page 23
The CPU has a register context consisting wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register ...
Page 24
Interrupt System With an interrupt response time within a range from just CPU clocks (in case of internal program execution), the C161CS/JC/JI is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of ...
Page 25
Table 3 C161CS/JC/JI Interrupt Nodes Source of Interrupt or PEC Service Request CAPCOM Register 0 CAPCOM Register 1 CAPCOM Register 2 CAPCOM Register 3 CAPCOM Register 4 CAPCOM Register 5 CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM ...
Page 26
Table 3 C161CS/JC/JI Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request CAPCOM Register 30 CAPCOM Register 31 CAPCOM Timer 0 CAPCOM Timer 1 CAPCOM Timer 7 CAPCOM Timer 8 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 ...
Page 27
The C161CS/JC/JI also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to ...
Page 28
Capture/Compare (CAPCOM) Units The CAPCOM units support generation and control of timing sequences channels with a maximum resolution of 16 TCL. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse ...
Page 29
When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode CPU TxIN GPT2 Timer T6 Over/Underflow CCxIO 8 Capture ...
Page 30
General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or ...
Page 31
T2EUD CPU T2IN CPU T3IN T3EUD T4IN CPU T4EUD … 10 Figure 6 Block Diagram of GPT1 With its maximum resolution of ...
Page 32
This allows the C161CS/JC/JI to measure absolute time differences or to perform pulse multiplication without software overhead. The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3’s inputs T3IN ...
Page 33
Real Time Clock The Real Time Clock (RTC) module of the C161CS/JC/JI consists of a chain of 3 divider blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible via registers RTCH and RTCL). ...
Page 34
A/D Converter For analog signal measurement, a 10-bit A/D converter with 12 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and ...
Page 35
Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by three serial interfaces with different functionality, two Asynchronous/Synchronous Serial Channels (ASC0/ASC1) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible with ...
Page 36
Serial Data Link Module (SDLM) The Serial Data Link Module (SDLM) provides serial communication via a J1850 type multiplexed serial bus via an external J1850 bus transceiver. The module conforms to the SAE Class B J1850 specification for variable pulse ...
Page 37
CAN-Modules The integrated CAN-Modules handle the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2.0 part B (active), i.e. the on-chip CAN-Modules can receive and transmit standard frames with 11-bit identifiers as well as ...
Page 38
Parallel Ports The C161CS/JC/JI provides I/O lines which are organized into eight input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction ...
Page 39
Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can ...
Page 40
Power Management The C161CS/JC/JI provides several means to control the power it consumes either at a given time or averaged over a certain timespan. Three mechanisms can be used (partly in parallel): • Power Saving Modes switch the C161CS/JC/JI into ...
Page 41
Instruction Set Summary Table 6 lists the instructions of the C161CS/JC/ condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the ...
Page 42
Table 6 Instruction Set Summary (cont’d) Mnemonic Description MOV(B) Move word (byte) data MOVBS Move byte operand to word operand with sign extension MOVBZ Move byte operand to word operand. with zero extension JMPA, JMPI, Jump absolute/indirect/relative ...
Page 43
Special Function Registers Overview Table 7 lists all SFRs which are implemented in the C161CS/JC/JI in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter ...
Page 44
Table 7 C161CS/JC/JI Registers, Ordered by Name (cont’d) Name Physical Address C1PCIR EF02 H C1LARn EFn4 H C1LGML EF0A H C1LMLM EF0E H C1MCFGn EFn6 H C1MCRn EFn0 H C1UARn EFn2 H C1UGML EF08 H C1UMLM EF0C H C2BTR EE04 ...
Page 45
Table 7 C161CS/JC/JI Registers, Ordered by Name (cont’d) Name Physical Address CC13IC b FF92 H CC14 FE9C H CC14IC b FF94 H CC15 FE9E H CC15IC b FF96 H CC16 FE60 H CC16IC b F160 H CC17 FE62 H CC17IC ...
Page 46
Table 7 C161CS/JC/JI Registers, Ordered by Name (cont’d) Name Physical Address CC28IC b F178 H CC29 FE7A H CC29IC b F184 H CC2IC b FF7C H CC3 FE86 H CC30 FE7C H CC30IC b F18C H CC31 FE7E H CC31IC ...
Page 47
Table 7 C161CS/JC/JI Registers, Ordered by Name (cont’d) Name Physical Address CRIC b FF6A H CSP FE08 H DP0H b F102 H DP0L b F100 H DP1H b F106 H DP1L b F104 H DP2 b FFC2 H DP3 b ...
Page 48
Table 7 C161CS/JC/JI Registers, Ordered by Name (cont’d) Name Physical Address IDPROG F078 H IFR EB18 H INTCON EB2C H IPCR EB04 H ISNC F1DE H MDC b FF0E H MDH FE0C H MDL FE0E H ODP2 b F1C2 H ...
Page 49
Table 7 C161CS/JC/JI Registers, Ordered by Name (cont’d) Name Physical Address PECC7 FECE H PICON b F1C4 H POCON0H F082 H POCON0L F080 H POCON1H F086 H POCON1L F084 H POCON2 F088 H POCON20 F0AA H POCON3 F08A H POCON4 ...
Page 50
Table 7 C161CS/JC/JI Registers, Ordered by Name (cont’d) Name Physical Address RXD18 EB58 H S0BG FEB4 H S0CON b FFB0 H S0EIC b FF70 H S0RBUF FEB2 H S0RIC b FF6E H S0TBIC b F19C H S0TBUF FEB0 H S0TIC ...
Page 51
Table 7 C161CS/JC/JI Registers, Ordered by Name (cont’d) Name Physical Address SYSCON b FF12 H SYSCON1 b F1DC H SYSCON2 b F1D0 H SYSCON3 b F1D4 H T0 FE50 H T01CON b FF50 H T0IC b FF9C H T0REL FE54 ...
Page 52
Table 7 C161CS/JC/JI Registers, Ordered by Name (cont’d) Name Physical Address T8 F052 H T8IC b F17C H T8REL F056 H TFR b FFAC H TRANSSTAT EB1E H TXCNT EB3C H TXCPU EB3E H TXD0 EB30 H TXD10 EB3A H ...
Page 53
Absolute Maximum Ratings Table 8 Absolute Maximum Rating Parameters Parameter Storage temperature Junction temperature V Voltage on pins with DD respect to ground ( Voltage on any pin with V respect to ground ( ) SS Input ...
Page 54
... > < > 0 C161CS/JC/JI-32R C161CS/JC/JI-L Unit Notes V Active mode MHz CPUmax V PowerDown mode V Reference voltage 2)3)4) mA Per pin Pin drivers in fast edge mode C SAB-C161CS/JC/JI … C SAF-C161CS/JC/JI … C SAK-C161CS/JC/JI … - 0.5 V). The absolute sum of input overload V3.0, 2001-01 5) ...
Page 55
Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C161CS/ JC/JI and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in ...
Page 56
DC Characteristics (cont’d) (Operating Conditions apply) Parameter Output low voltage (all other outputs) 5) Output high voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) 5) Output high voltage (all other outputs) Input leakage current (Port 5) Input ...
Page 57
These parameters describe the RSTIN pullup, which equals a resistance of ca 250 The maximum current may be drawn while the respective signal line remains inactive. 8) The minimum current must be drawn in ...
Page 58
I µA 1500 1250 1000 750 500 250 I IDOAmax 0 0 Figure 9 Idle and Power Down Supply Current as a Function of Oscillator Frequency Data Sheet I IDOMmax I IDOMtyp I PDRMmax I PDOmax C161CS/JC/JI-32R ...
Page 59
I [mA] 100 Figure 10 Supply/Idle Current as a Function of Operating Frequency Data Sheet C161CS/JC/JI-32R C161CS/JC/JI-L I DD5max I DD5typ I IDX5max I IDX5typ 25 f [MHz] CPU V3.0, 2001-01 ...
Page 60
AC Characteristics Definition of Internal Timing The internal operation of the C161CS/JC/JI is controlled by the internal CPU clock Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the ...
Page 61
P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register RSTCON under software control. Table 10 associates the combinations of these three bits with the respective clock generation mode. Table 10 C161CS/JC/JI Clock Generation Modes CLKCFG CPU ...
Page 62
The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL. As ...
Page 63
Direct Drive When direct drive is configured (CLKCFG = 011 disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. f The frequency of directly follows the frequency of CPU f (i.e. the ...
Page 64
AC Characteristics External Clock Drive XTAL1 (Main Oscillator) (Operating Conditions apply) Table 11 External Clock Drive Characteristics Parameter Symbol t Oscillator period OSCM 2) High time Low time 2 2) Rise time ...
Page 65
AC Characteristics External Clock Drive XTAL3 (Auxiliary Oscillator) (Operating Conditions apply) Table 12 AC Characteristics Parameter Symbol t Oscillator period OSCA High time Low time 2 Rise time Fall time 4 1) The clock ...
Page 66
A/D Converter Characteristics (Operating Conditions apply) Table 13 A/D Converter Characteristics Parameter Analog reference supply Analog reference ground Analog input voltage range Basic clock frequency Conversion time Calibration time after reset Total unadjusted error Internal resistance of reference voltage source ...
Page 67
During the sample time the input capacitance internal resistance of the analog source must allow the capacitance to reach its final voltage level within After the end of the sample time result. Values for the sample time t S ...
Page 68
Testing Waveforms 2 inputs during testing are driven at 2.4 V for a logic 1’ and 0.45 V for a logic 0’. Timing measurements are made at Figure 14 Input Output Waveforms V + 0.1 V ...
Page 69
Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Table 15 ...
Page 70
Multiplexed Bus (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 Parameter RD, WR low time (no RW-delay valid data in (with RW-delay valid data in (no RW-delay) ALE low to valid data ...
Page 71
Multiplexed Bus (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 Parameter ALE fall. edge to RdCS, WrCS (no RW delay) Address float after RdCS, WrCS (with RW delay) Address float after RdCS, WrCS (no RW delay) ...
Page 72
ALE CSxL A23-A16 (A15-A8) BHE, CSxE Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 16 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE Data Sheet ...
Page 73
ALE CSxL A23-A16 (A15-A8) BHE, CSxE t 6 Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 17 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Data Sheet ...
Page 74
ALE CSxL A23-A16 (A15-A8) BHE, CSxE Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 18 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE Data Sheet ...
Page 75
ALE CSxL A23-A16 (A15-A8) BHE, CSxE t 6 Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 19 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE Data Sheet ...
Page 76
AC Characteristics Demultiplexed Bus (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) RD, ...
Page 77
Demultiplexed Bus (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter Data valid to WR Data hold after WR ALE rising edge after RD Address hold after WR 3) ALE falling edge to CS ...
Page 78
Demultiplexed Bus (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter Data float after RdCS 1) (no RW-delay) Address hold after RdCS, WrCS Data hold after WrCS 1) RW-delay and t refer to the next following ...
Page 79
ALE CSxL A23-A16 A15-A0 BHE, CSxE Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 20 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE Data Sheet ...
Page 80
ALE CSxL A23-A16 A15-A0 BHE, CSxE t 6 Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 21 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE Data Sheet ...
Page 81
ALE CSxL A23-A16 A15-A0 BHE, CSxE Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 22 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Data Sheet ...
Page 82
ALE CSxL A23-A16 A15-A0 BHE, CSxE t 6 Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 23 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE Data Sheet ...
Page 83
AC Characteristics CLKOUT and READY (Operating Conditions apply) Parameter CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge Synchronous READY setup time to CLKOUT Synchronous READY hold ...
Page 84
CLKOUT ALE Command RD, WR Sync READY t 58 Async 3) READY Figure 24 CLKOUT and READY Notes 1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). 2) The leading edge of the respective command depends on ...
Page 85
AC Characteristics External Bus Arbitration (Operating Conditions apply) Parameter HOLD input setup time to CLKOUT CLKOUT to HLDA high or BREQ low delay CLKOUT to HLDA low or BREQ high delay CSx release CSx drive Other signals release Other signals ...
Page 86
CLKOUT t 61 HOLD HLDA see BREQ CSx (On P6.x) Other Signals Figure 25 External Bus Arbitration, Releasing the Bus Notes 1) The C161CS/JC/JI will complete the currently running bus cycle before granting bus access. 2) This is the first ...
Page 87
CLKOUT HOLD HLDA t 62 BREQ CSx (On P6.x) Other Signals Figure 26 External Bus Arbitration, (Regaining the Bus) Notes 1) This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the ...
Page 88
Package Outline P-TQFP-128-2 (Plastic Thin Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Sheet C161CS/JC/JI-32R 84 C161CS/JC/JI-L Dimensions in mm V3.0, ...
Page 89
... Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction.” Dr. Ulrich Schumacher Published by Infineon Technologies AG ...