SAF-XC167CI-32F40F BB-A Infineon Technologies, SAF-XC167CI-32F40F BB-A Datasheet - Page 79
![IC MCU 16BIT 256KB TQFP-144-19](/photos/39/69/396957/qfp144_sml.jpg)
SAF-XC167CI-32F40F BB-A
Manufacturer Part Number
SAF-XC167CI-32F40F BB-A
Description
IC MCU 16BIT 256KB TQFP-144-19
Manufacturer
Infineon Technologies
Series
XC16xr
Datasheet
1.SAF-XC167CI-32F20F_BB-A.pdf
(90 pages)
Specifications of SAF-XC167CI-32F40F BB-A
Core Processor
C166SV2
Core Size
16-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
PWM, WDT
Number Of I /o
103
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.7 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFQFP
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
2xASC, 2xSSC, 1xI2C
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
103
Number Of Timers
11
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Packages
PG-TQFP-144
Max Clock Frequency
40.0 MHz
Sram (incl. Cache)
12.0 KByte
Can Nodes
2
A / D Input Lines (incl. Fadc)
16
Program Memory
256.0 KByte
For Use With
B158-H8963-X-X-7600IN - KIT EASY XC167CIMCBX167-NET - BOARD EVAL INFINEON CAN/ETHRNTMCBXC167-BASIC - BOARD EVAL BASIC INFINEON XC16X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
FX167CI32F40FBBANT
SAFXC167CI32F40FBBAT
SP000104964
SP000224702
SAFXC167CI32F40FBBAT
SP000104964
SP000224702
Table 22
Parameter
Output valid delay for:
RD, WR(L/H)
Output valid delay for:
A23 … A16, BHE, ALE
Output valid delay for:
A15 … A0 (on PORT1)
Output valid delay for:
A15 … A0 (on PORT0)
Output valid delay for:
CS
Output valid delay for:
D15 … D0 (write data, MUX-mode)
Output valid delay for:
D15 … D0 (write data, DEMUX-mode)
Output hold time for:
RD, WR(L/H)
Output hold time for:
A23 … A16, BHE, ALE
Output hold time for:
A15 … A0 (on PORT0)
Output hold time for:
CS
Output hold time for:
D15 … D0 (write data)
Input setup time for:
READY, D15 … D0 (read data)
Input hold time
READY, D15 … D0 (read data)
1) Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge
Note: The shaded parameters have been verified by characterization.
Data Sheet
of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles. Read
data can be removed after the rising edge of RD.
They are not subject to production test.
External Bus Cycle Timing (Operating Conditions apply)
1)
77
Symbol
tc
tc
tc
tc
tc
tc
tc
tc
tc
tc
tc
tc
tc
tc
10
11
12
13
14
15
16
20
21
23
24
25
30
31
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
SR
SR
Min.
1
-1
3
3
3
3
2
-3
0
1
-2
1
29
-5
Electrical Parameters
Limits
Max.
15
8
18
18
16
19
16
4
11
13
4
13
–
–
XC167CI-32F
Derivatives
V1.1, 2006-08
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns