SAF-XC167CI-32F40F BB-A Infineon Technologies, SAF-XC167CI-32F40F BB-A Datasheet - Page 23
![IC MCU 16BIT 256KB TQFP-144-19](/photos/39/69/396957/qfp144_sml.jpg)
SAF-XC167CI-32F40F BB-A
Manufacturer Part Number
SAF-XC167CI-32F40F BB-A
Description
IC MCU 16BIT 256KB TQFP-144-19
Manufacturer
Infineon Technologies
Series
XC16xr
Datasheet
1.SAF-XC167CI-32F20F_BB-A.pdf
(90 pages)
Specifications of SAF-XC167CI-32F40F BB-A
Core Processor
C166SV2
Core Size
16-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
PWM, WDT
Number Of I /o
103
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.7 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFQFP
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
2xASC, 2xSSC, 1xI2C
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
103
Number Of Timers
11
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Packages
PG-TQFP-144
Max Clock Frequency
40.0 MHz
Sram (incl. Cache)
12.0 KByte
Can Nodes
2
A / D Input Lines (incl. Fadc)
16
Program Memory
256.0 KByte
For Use With
B158-H8963-X-X-7600IN - KIT EASY XC167CIMCBX167-NET - BOARD EVAL INFINEON CAN/ETHRNTMCBXC167-BASIC - BOARD EVAL BASIC INFINEON XC16X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
FX167CI32F40FBBANT
SAFXC167CI32F40FBBAT
SP000104964
SP000224702
SAFXC167CI32F40FBBAT
SP000104964
SP000224702
3
The architecture of the XC167 combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a very well-balanced way. In
addition, the on-chip memory blocks allow the design of compact systems-on-silicon with
maximum performance (computing, control, communication).
The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data
SRAM) and the set of generic peripherals are connected to the CPU via separate buses.
Another bus, the LXBus, connects additional on-chip resources as well as external
resources (see
This bus structure enhances the overall system performance by enabling the concurrent
operation of several subsystems of the XC167.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the XC167.
Figure 3
Data Sheet
X T A L
P 20
C hannels
C lo ck G e n e ra tio n
8/10-B it
ADC
D e b u g S u p p o rt
Functional Description
O sc / PLL
16
6
O CDS
P ort 9
128 KB ytes
ProgM em
Block Diagram
PSRAM
Figure
6
F la sh
G PT
P 7
T 2
T 3
T 4
T 5
T 6
4
P ort 6
(U S A R T )
ASC0
B R G en
3).
RTC
8
(U S A R T )
ASC1
W DT
B R G en
P ort 5
16
SSC0
B R G en
(S P I)
P ort 4
SSC1
C166SV2-Core
8
B R G en
(S P I)
Interrupt & PEC
21
DPRAM
CPU
P ort 3
CC1
T 0
T 1
15
CC2
T 7
T 8
P ort 2
P e rip he ral D ata B us
Interrupt B us
8
B R G en
IIC
Functional Description
P O R T 1
16
CC6
T 12
T 13
X B U S C on trol
E xtern al B u s
DSRAM
C ontrol
XC167CI-32F
EBC
M C B 04323_x7.vsd
Derivatives
V1.1, 2006-08
P O R T 0
Tw in
CAN
A
16
B