SAF-C161O-LM HA Infineon Technologies, SAF-C161O-LM HA Datasheet - Page 57
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SAF-C161O-LM HA
Manufacturer Part Number
SAF-C161O-LM HA
Description
IC MCU 16BIT ROM/LESS MQFP-80-1
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet
1.SAF-C161O-L25M_HA.pdf
(66 pages)
Specifications of SAF-C161O-LM HA
Core Processor
C166
Core Size
16-Bit
Speed
20MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
63
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-SQFP
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
ASC, SSC
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
63
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
SAF-C161O-LMHA
SAF-C161O-LMHAINTR
SAF-C161O-LMHATR
SAF-C161O-LMHATR
SAFC161OLMHAXT
SP000011623
SAF-C161O-LMHAINTR
SAF-C161O-LMHATR
SAF-C161O-LMHATR
SAFC161OLMHAXT
SP000011623
Demultiplexed Bus (Standard Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
Parameter
Data float after RdCS
(with RW-delay)
Data float after RdCS
(no RW-delay)
Address hold after
RdCS, WrCS
Data hold after WrCS
1)
2)
3)
Data Sheet
RW-delay and
Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
t
1)
A
1)
refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
Symbol
t
t
t
t
53
68
55
57
t
A
+
CC -6 +
CC 6 +
SR –
SR –
t
C
+
min.
t
F
Max. CPU Clock
(80 ns at 25 MHz CPU clock without waitstates)
t
t
F
= 25 MHz
F
53
max.
20 +
0 +
–
–
t
F
t
F
1 / 2TCL = 1 to 25 MHz
min.
–
–
-6 +
TCL - 14
+
Variable CPU Clock
t
F
t
F
max.
2TCL - 20
+ 2
1)
TCL - 20
+ 2
1)
–
–
t
t
A
A
V2.0, 2001-01
+
+
t
t
F
F
C161O
C161K
Unit
ns
ns
ns
ns