SAF-C161O-LM HA Infineon Technologies, SAF-C161O-LM HA Datasheet - Page 13
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SAF-C161O-LM HA
Manufacturer Part Number
SAF-C161O-LM HA
Description
IC MCU 16BIT ROM/LESS MQFP-80-1
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet
1.SAF-C161O-L25M_HA.pdf
(66 pages)
Specifications of SAF-C161O-LM HA
Core Processor
C166
Core Size
16-Bit
Speed
20MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
63
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-SQFP
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
ASC, SSC
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
63
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
SAF-C161O-LMHA
SAF-C161O-LMHAINTR
SAF-C161O-LMHATR
SAF-C161O-LMHATR
SAFC161OLMHAXT
SP000011623
SAF-C161O-LMHAINTR
SAF-C161O-LMHATR
SAF-C161O-LMHATR
SAFC161OLMHAXT
SP000011623
Functional Description
The architecture of the C161K/O combines advantages of both RISC and CISC
processors and of advanced peripheral subsystems in a very well-balanced way. In
addition the on-chip memory blocks allow the design of compact systems with maximum
performance.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the C161K/O.
Note: All time specifications refer to a CPU clock of 25 MHz
Figure 3
The program memory, the internal RAM (IRAM) and the set of generic peripherals are
connected to the CPU via separate buses. A fourth bus, the XBUS, connects external
resources as well as additional on-chip resources, the X-Peripherals (see
Data Sheet
8
8
(see definition in the AC Characteristics section).
ProgMem
Internal
ROM
Area
XBUS Control
External Bus
Port 0
Block Diagram
Control
16
EBC
Instr. / Data
16
16
Port 1
32
16
External Instr. / Data
(USART)
ASC0
BRGen
Interrupt Controller 16-Level
Port 3
C166-Core
CPU
BRGen
SSC
(SPI)
15
9
PEC
Priority
GPT1
T2
T3
T4
Interrupt Bus
GPT2
Peripheral Data Bus
T5
T6
Data
Data
16
Port 5
16
16
6
1/2 Kbyte
Osc
Internal
IRAM
MCB04323_1ko
RAM
Figure
V2.0, 2001-01
WDT
C161O
C161K
3).
XTAL
8