DS89C420-QCL Maxim Integrated Products, DS89C420-QCL Datasheet - Page 34
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DS89C420-QCL
Manufacturer Part Number
DS89C420-QCL
Description
IC MCU ULTRA 33MHZ HP 44-PLCC
Manufacturer
Maxim Integrated Products
Series
89Cr
Datasheet
1.DS89C420-QCS.pdf
(47 pages)
Specifications of DS89C420-QCL
Core Processor
8051
Core Size
8-Bit
Speed
33MHz
Connectivity
EBI/EMI, SIO, UART/USART
Peripherals
Power-Fail Reset, WDT
Number Of I /o
32
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
44-LCC, 44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS89C420-QCL
Manufacturer:
PHI
Quantity:
6 217
Company:
Part Number:
DS89C420-QCL
Manufacturer:
Maxim Integrated
Quantity:
10 000
Figure 14. Page Mode 1, External Data Memory Access (Pages = 01, Stretch = 4, CD = 10)
Figure 14
memory cycle is shorter than a page miss data-memory cycle. The ALE pulse width is also stretched by a stretch
cycle in the case of page miss.
The stretched data-memory bus-cycle timing relationship for PAGES = 11 is identical to non-page mode operation
since the basic data-memory cycle always contains four system clocks in this page mode operation.
INTERRUPTS
The DS89C420 provides 13 interrupt vector sources. All interrupts, with the exception of the power-fail, are
controlled by a series combination of individual enable bits and a global enable (EA) in the interrupt enable register
(IE.7). Setting EA to logic 1 allows individual interrupts to be enabled. Setting EA to a logic 0 disables all interrupts
RD / WR
RD / WR
XTAL1
PSEN
Port 0
Port 2
PSEN
Port 0
Port 2
ALE
ALE
shows the timing relationship for a slow peripheral interface (stretch value = 4). Note that a page hit data-
LSB LSB
LSB
Inst
Inst
Instruction
Instruction
LSB
Inst
MOVX
Inst
MOVX
Fetch
Fetch
LSB
LSB
Inst
Inst
Cycle
Cycle
LSB
LSB
1st
1st
Inst
Inst
Cycle
2nd
Cycle
2nd
MSB
Cycle
3rd
Cycle
3rd
34 of 47
MOVX Instruction (Page miss)
MOVX Instruction (Page hit)
Memory Access (Stretch = 4)
Memory Access (Stretch = 4)
Cycle
4th
Cycle
4th
Cycle
5th
Cycle
Data
LSB
9th
Data
LSB
Cycle
9th
LSB LSB LSB
Inst
LSB LSB
Inst
Inst
Inst
Inst