R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 213

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

7.5.5
When information on 1- or 4-Kbyte pages is written as TLB entries, a synonym problem may
arise. The problem is that, when a number of virtual addresses are mapped onto a single physical
address, the same physical address data is written to a number of cache entries, and it becomes
impossible to guarantee data integrity. This problem does not occur with the instruction TLB and
instruction cache because only data is read in these cases. In this LSI, entry specification is
performed using bits 12 to 5 of the virtual address in order to achieve fast operand cache
operation. However, bits 12 to 10 of the virtual address in the case of a 1-Kbyte page, and bit 12 of
the virtual address in the case of a 4-Kbyte page, are subject to address translation. As a result, bits
12 to 10 of the physical address after translation may differ from bits 12 to 10 of the virtual
address.
Consequently, the following restrictions apply to the writing of address translation information as
UTLB entries.
• When address translation information whereby a number of 1-Kbyte page UTLB entries are
• When address translation information whereby a number of 4-Kbyte page UTLB entries are
• Do not use 1-Kbyte page UTLB entry physical addresses with UTLB entries of a different
• Do not use 4-Kbyte page UTLB entry physical addresses with UTLB entries of a different
The above restrictions apply only when performing accesses using the cache.
translated into the same physical address is written to the UTLB, ensure that the VPN[12:10]
values are the same.
translated into the same physical address is written to the UTLB, ensure that the VPN[12]
value is the same.
page size.
page size.
Avoiding Synonym Problems
Rev.1.00 Jan. 10, 2008 Page 181 of 1658
7. Memory Management Unit (MMU)
REJ09B0261-0100