R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 1332

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

26. Serial Sound Interface (SSI) Module
26.3
The SSI has the following registers. In this manual, the register description is not discriminated
by the channel.
Table 26.2 Register Configuration (1)
Note: Bits 26 and 27 of this register is readable/writable. The other bits are read only. For
Table 26.2 Register Configuration (2)
Rev.1.00 Jan. 10, 2008 Page 1300 of 1658
REJ09B0261-0100
Channel
0
0
0
0
1
1
1
1
Channel
0
0
0
0
1
1
1
1
details, see section 26.3.2, Status Register (SSISR).
Register Descriptions
Register Name
Control register 0
Status register 0
Transmit data register 0
Receive data register 0
Control register 1
Status register 1
Transmit data register 1
Receive data register 1
Register Name
Control register 0
Status register 0
Transmit data
register 0
Receive data
register 0
Control register 1
Status register 1
Transmit data
register 1
Receive data
register 1
Abbrev.
SSISR0
SSITDR0
SSIRDR0
SSISR1
SSITDR1
SSIRDR1
SSICR0
SSICR1
Abbrev.
SSICR0
SSISR0
SSITDR0
SSIRDR0
SSICR1
SSISR1
SSITDR1
SSIRDR1
Power-on
Reset by
PRESET Pin/
WDT/H-UDI
H'0000 0000
H'0200 0003
H'0000 0000
H'0000 0000
H'0000 0000
H'0200 0003
H'0000 0000
H'0000 0000
R/W
R/W
R/W*
R/W
R
R/W
R/W*
R/W
R
Manual Reset
by WDT/
Multiple
Exception
H'0000 0000
H'0200 0003
H'0000 0000
H'0000 0000
H'0000 0000
H'0200 0003
H'0000 0000
H'0000 0000
P4 Address
H'FFE0 0000
H'FFE0 0004
H'FFE0 0008
H'FFE0 000C
H'FFE1 0000
H'FFE1 0004
H'FFE1 0008
H'FFE1 000C
Sleep by
SLEEP
Instruction
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Area 7
Address
H'1FE0 0000
H'1FE0 0004
H'1FE0 0008
H'1FE0 000C
H'1FE1 0000
H'1FE1 0004
H'1FE1 0008
H'1FE1 000C
Module
Standby
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Size
32
32
32
32
32
32
32
32
Deep
Sleep
Sync
Clock
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck