R5F21236JFP#U0 Renesas Electronics America, R5F21236JFP#U0 Datasheet - Page 286
![IC R8C/23 MCU FLASH 48LQFP](/photos/28/61/286102/48-lqfp__plqp0048kb-a_sml.jpg)
R5F21236JFP#U0
Manufacturer Part Number
R5F21236JFP#U0
Description
IC R8C/23 MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/R8C/Tiny/23r
Datasheet
1.R5F21237DFPU0.pdf
(551 pages)
Specifications of R5F21236JFP#U0
Core Processor
R8C
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21236JFP#U0R5F21236JFP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
R5F21236JFP#U0R5F21236JFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
R5F21236JFP#U0R5F21236JFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 14.111 Operation When TRD1 Register Underflows in Complementary PWM Mode
TRDGRB0 register
TRDGRA1 register
TRDGRB1 register
TRDSR0 register
TRDSR0 register
Count value in TRD0
UDF bit in
OVF bit in
•
The TRD1 register counts the order of 1, 0, FFFFh, 0, 1 when changing from decrement to increment.
The UDF bit is set to 1 by the order of 1, 0, FFFFh operation. Also, when the CMD1 to CMD0 bits in the
TRDFCR register are set to 10b (complementary PWM mode, buffer data transferred by the underflow in
the TRD1 register), the content in the buffer register (TRDGRD0, TRDGRC1, TRDGRD1) is transferred
to the general register (TRDGRB0, TRDGRA1, TRDGRB1). For the order of FFFFh, 0, 1 operation, data
are not transferred to the register such as the TRDGRB0 register. Also, at this time, the OVF bit remains
unchanged.
FFFFh
register
1
0
1
0
1
0
Set to 0 by a program
Page 264 of 501
Transferred from
buffer register
No change
Not transferred from buffer register
When the CMD1 to CMD0 bits in the
TRDFCR register are set to 10b.
(Transfer from the buffer register to the
general register when the TRD1 register
underflows)
14. Timers
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