MC908GR48AMFAE Freescale Semiconductor, MC908GR48AMFAE Datasheet - Page 220

• Manufacturer Part Number: MC908GR48AMFAE
• Description: IC MCU 8BIT 48K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR48AMFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Serial Peripheral Interface (SPI) Module
SPR1 and SPR0 — SPI Baud Rate Select Bits
15.12.3 SPI Data Register
The SPI data register consists of the read-only receive data register and the write-only transmit data
register. Writing to the SPI data register writes data into the transmit data register. Reading the SPI data
register reads data from the receive data register. The transmit data and receive data registers are
separate registers that can contain different values. See
R7–R0/T7–T0 — Receive/Transmit Data Bits
220
If the MODFEN bit is 0, the level of the SS pin does not affect the operation of an enabled SPI
configured as a master. For an enabled SPI configured as a slave, having MODFEN low only prevents
the MODF flag from being set. It does not affect any other part of SPI operation. See
Error.
In master mode, these read/write bits select one of four baud rates as shown in
SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0.
Use this formula to calculate the SPI baud rate:
Address: $0012
Do not use read-modify-write instructions on the SPI data register since the
register read is not the same as the register written.
Reset:
Read:
Write:
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Bit 7
R7
T7
Table 15-3. SPI Master Baud Rate Selection
SPR1 and SPR0
Figure 15-16. SPI Data Register (SPDR)
R6
T6
6
00
01
10
11
Baud rate =
R5
T5
5
NOTE
Unaffected by reset
R4
T4
4
BUSCLK
Baud Rate Divisor (BD)
Figure
BD
R3
T3
3
15-2.
128
32
2
8
R2
T2
2
R1
T1
1
Table
Freescale Semiconductor
15.6.2 Mode Fault
Bit 0
R0
T0
15-3. SPR1 and