MC908GR48AMFAE Freescale Semiconductor, MC908GR48AMFAE Datasheet - Page 189

• Manufacturer Part Number: MC908GR48AMFAE
• Description: IC MCU 8BIT 48K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR48AMFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Reset and System Initialization
OSC1
PORRST
4096
32
32
CYCLES
CYCLES
CYCLES
CGMXCLK
CGMOUT
RST
IAB
$FFFE
$FFFF
Figure 14-7. POR Recovery
14.3.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP
bit in the SIM reset status register (SRSR) and causes a reset.
If the stop enable bit, STOP, in the CONFIG1 register is 0, the SIM treats the STOP instruction as an
illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal
reset sources.
14.3.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the
CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively
pulls down the RST pin for all internal reset sources.
14.3.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when the V
voltage falls to the V
DD
TRIPF
voltage. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin (RST) is
asserted if the LVIPWRD and LVIRSTD bits in the CONFIG1 register are 0. The RST pin will be held low
while the SIM counter counts out 4096 + 32 CGMXCLK cycles after V
rises above V
. Thirty-two
DD
TRIPR
CGMXCLK cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The
SIM actively pulls down the RST pin for all internal reset sources.
14.3.2.6 Monitor Mode Entry Module Reset (MODRST)
The monitor mode entry module reset (MODRST) asserts its output to the SIM when monitor mode is
entered in the condition where the reset vectors are erased ($FF) (see
19.3.1.1 Normal Monitor
Mode).
When MODRST gets asserted, an internal reset occurs. The SIM actively pulls down the RST pin for all
internal reset sources.
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Freescale Semiconductor
189