MC9S12UF32PB Freescale Semiconductor, MC9S12UF32PB Datasheet - Page 78

• Manufacturer Part Number: MC9S12UF32PB
• Description: IC MCU 32K FLASH 30MHZ 64LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12UF32PB

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 30MHz
• Connectivity: ATA, Compact Flash, EBI/EMI, Memory Stick, MMC, SCI, SD, Smart Media, USB
• Peripherals: POR, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 3.5K x 8
• Voltage - Supply (vcc/vdd): 2.25 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

System on a Chip Guide — 9S12UF32DGV1/D V01.05
Section 4 Modes of Operation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12UF32. Each mode has an
associated default memory map and external bus configuration. In addition each operating mode, with the
exception of Special Peripheral Mode (SPM), can be configured for low power operation by entering one
of two low power sub-modes. The device is also equipped with security features which restrict certain
modes of operation and limit access to internal memory. More detailed information on the various
operating modes, and their configurations can be found in the HCS12 V1.5 Core User Guide.
4.2 Modes of Operation
There are two basic categories of operating modes:
In all Normal and Special modes a system development and debug feature, background debug mode
(BDM), is available. In special single-chip mode, BDM is active immediately after reset.
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset (Table 4-1). The MODC, MODB, and MODA bits in the MODE register show the current operating
mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA
pins are latched into these bits on the rising edge of the reset signal. When resetting into all modes except
SPM, the ESTR bit in the EBICTL register is set to one, configuring the ECLK as a bus control signal, to
assure that the reset vector can be fetched even if it located in an external slow memory device.
The following sections discuss the default bus setup and describe which aspects of the bus can be changed
after reset on a per mode basis.
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1. Normal modes: Some registers and bits are protected against accidental changes.
2. Special modes: Allow greater access to protected control registers and bits for special purposes such
as testing.
BKGD =
MODC
0
0
0
0
1
1
1
1
MODB
PE6 =
0
0
1
1
0
0
1
1
MODA
PE5 =
0
1
0
1
0
1
0
1
Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all
other modes but a serial command is required to make BDM active.
Emulation Expanded Narrow, BDM allowed
Special Test (Expanded Wide), BDM allowed
Emulation Expanded Wide, BDM allowed
Normal Single Chip, BDM allowed
Normal Expanded Narrow, BDM allowed
Special Peripheral; BDM allowed but bus operations would cause bus
conflicts (must not be used)
Normal Expanded Wide, BDM allowed
Table 4-1 Mode Selection
Mode Description
Freescale Semiconductor