MC9S12UF32PB Freescale Semiconductor, MC9S12UF32PB Datasheet - Page 3

• Manufacturer Part Number: MC9S12UF32PB
• Description: IC MCU 32K FLASH 30MHZ 64LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12UF32PB

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 30MHz
• Connectivity: ATA, Compact Flash, EBI/EMI, Memory Stick, MMC, SCI, SD, Smart Media, USB
• Peripherals: POR, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 3.5K x 8
• Voltage - Supply (vcc/vdd): 2.25 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

Freescale Semiconductor
Release
Number
01.00
01.01
01.02
01.03
01.04
01.05
23MAR04
21AUG03
28NOV03
20APR04
10MAY04
03DEC04
Date
Wai-On Law
Wai-On Law
Wai-On Law
Wai-On Law
Y.H. Cheng
Y.H. Cheng
Author
- Removed all references to XCLKS, since function is removed.
- typo - replaced PRU with RPU.
- typo - replaced ATAHC with ATA5HC
- Removed references to clock monitor, since function is not
available.
- Update
- Add footnotes on IRQ pin removal in 64-pin package
- Update Flash memory map out of reset.
- Add information on INITRM, INITRG, INITEE setting for example
application memory map
- Update clock distribution diagram to make it more intelligible
- Change table 2-3, 2-5 description using general purpose port
references instead of Functional module references.
- Stop IDD spec for -40C and 85C are removed
- Add other conditions for RUN Idd and Wait Idd.
- Minor typo corrections.
- Corrected ‘Background Debug Module’ to ‘HCS12 Breakpoint’ at
address $0028-$002F in table 1-1.
- Added detailed register map.
- Corrected the MSHC enable control in table 5-1.
- Added part ID $6311 for mask 1L47S.
- Removed all references and description on USB Physical
Endpoint 6
- Updated IDD, 3V and 5V I/O electricals and package thermal
resistance information
- Include Commercial tier note
- Update and add note to detailed register map.
- Added PIM reference.
- Added package information as appendix B.
- Improved fig 1-1.
- Fixed consistency of 3.0v and 3.3v for VDD3X.
- Updated power dissipation formula.
- Added schematic and PCB layout recommendations.
- Added NVM, VREGU, CRGU electricals to appendix A.
JA
System on a Chip Guide — 9S12UF32DGV1/D V01.05
for 100-pin and 64-pin packages.
Summary of Changes
3