MC9S12UF32PB Freescale Semiconductor, MC9S12UF32PB Datasheet - Page 53

• Manufacturer Part Number: MC9S12UF32PB
• Description: IC MCU 32K FLASH 30MHZ 64LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12UF32PB

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 30MHz
• Connectivity: ATA, Compact Flash, EBI/EMI, Memory Stick, MMC, SCI, SD, Smart Media, USB
• Peripherals: POR, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 3.5K x 8
• Voltage - Supply (vcc/vdd): 2.25 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

Freescale Semiconductor
Pin Name
Function
NOTES:
1. This pin must be tied to VSS in Application
2. CFHC module port routing when bit 4 of MODRR is set to 1.
3. PJ2 is used as the ROMCTL signal during reset.
PR[7:4]
PT[0:2]
PR[2]
PR[3]
PT[3]
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
PU5
PU4
PU3
PU2
PU1
PU0
1
Pin Name
CFINPACK ATADMACK
Function
CFA[10:7]
CFIOIS16
CFIOWR
CFWAIT
CFRDY/
IOC[0:2]
CFREG
CFCE2
CFCE1
CFIORD
CFA[5]
CFA[6]
CFWE
IOC[3]
CFOE
IREQ
CFA2
CFA1
CFA0
2
ATADMARQ
Pin Name
ATAIORDY
Function
ATAIOWR
CFA[0:2]
ATAINTQ
ATAIORD
IOC[7:4]
ATACS1
ATACS0
ATADA2
ATADA1
ATADA0
CFWE
RXD
TXD
—
—
—
3
2
2
Pin Name
Function
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
Supply
VDD3X
VDD3X
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
Rail
System on a Chip Guide — 9S12UF32DGV1/D V01.05
CTRL
PERS/
PERS/
PERS/
PERS/
PERS/
PERS/
PERS/
PERS/
PERT/
PERT/
PERU/
PERU/
PERU/
PERU/
PERU/
PERU/
PERR
PPSR
PERR
PPSR
PERR
PPSR
PPSS
PPSS
PPSS
PPSS
PPSS
PPSS
PPSS
PPSS
PPSU
PPSU
PPSU
PPSU
PPSU
PPSU
PPST
PPST
Internal Pull
Resistor
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled Port S I/O Pin; CFHC OE signal
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled Port U I/O Pins; CFHC REG signal
Disabled
Disabled
Reset
State
Port R I/O Pin; CFHC address line,
SCI RXD
Port R I/O Pin; CFHC address line,
SCI TXD
Port R I/O Pins; CFHC address
lines, Timer Channel 4 to 7
Port S I/O Pin; CFHC RDYIREQ
signal; ATA INTQ signal
Port S I/O Pin; CFHC WE signal;
ATA DMARQ signal
Port S I/O Pin; CFHC IOWR signal;
ATA IOWR signal
Port S I/O Pin; CFHC IORD signal;
ATA IORD signal
Port S I/O Pin; CFHC CE2 signal;
ATA CS2 signal
Port S I/O Pin; CFHC IOIS16
signal
Port S I/O Pin; CFHC CE1 signal;
ATA CS0 signal
Port T I/O Pins; Timer channels 0
to 2; CFHC address line
Port T I/O Pins; Timer channels 3;
CFHCWE signal
Port U I/O Pins; CFHC Address
signal; ATA Address signal
Port U I/O Pins; CFHC Address
signal; ATA Address signal
Port U I/O Pins; CFHC Address
signal; ATA Address signal
Port U I/O Pins; CFHC INPACK
signal; ATA DMACK signal
Port U I/O Pins; CFHC WAIT
signal; ATA IORDY signal
Description
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