M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 52

• Manufacturer Part Number: M30802FCGP#D3
• Description: IC M16C MCU FLASH 128K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802FCGP#D3

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

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Table 7.10 Operation of RAS, CASL, CASH, and DW signals
6
1 .
0
(9) DRAM controller signals (RAS, CASL, CASH, and DW)
(10) Software wait
C
Data bus width
9
0 .
8 /
Bits 1, 2, and 3 of the DRAM control register (address 0004
DRAM controller. The DRAM controller signals are then output when the DRAM area is accessed. Table
7.10 shows the operation of the respective signals.
A software wait can be inserted by setting the wait control register (address 0008
wait control register
You can use the external area I wait bits (where I = 0 to 3) of the wait control register to specify from “No
wait” to “3 waits” for the external memory area. When you select “No wait”, the read cycle is executed in
the BCLK1 cycle. The write cycle is executed in the BCLK2 cycle (which has 1 wait). When accessing
external memory using the multiplex bus, access has two waits regardless of whether you specify “No
wait” or “1 wait” in the appropriate external area i wait bits in the wait control register.
Software waits in the internal memory (internal RAM and internal ROM) can be set using the internal
memory wait bits of the processor mode register 1 (address 0005
= “0” sets “No wait”. Setting the internal memory wait bit = “1” specifies a wait.
The SFR area is not affected by the setting of the internal memory wait bit and is always accessed in the
BCLK2 cycle.
Table 7.11 shows the software waits and bus cycles. Figures 7.7 and 7.8 show example bus timings
when using software waits.
B
0
0
0
1
16-bit
8-bit
A
G
8
u
7
o r
. g
0 -
u
1
0
p
0
, 2
0
2
0
0
5
RAS
Page 39
L
L
L
L
L
L
L
L
_______
CASL
f o
__________
H
H
L
L
L
L
L
L
3
2
9
_______
__________
Not used
Not used
CASH
H
H
L
L
L
L
__________
_____
DW
__________
H
H
H
H
L
L
L
L
Read data from both even and odd addresses
Read 1 byte of data from even address
Write data to both even and odd addresses
Write 1 byte of data to odd address
Read 1 byte of data
Write 1 byte of data
Read 1 byte of data from odd address
Write 1 byte of data to even address
16
) select the DRAM space and enable the
16
). Setting the internal memory wait bit
_____
Status of external data bus
16
). Figure 7.6 shows
7. Bus