HD64F2636F20J Renesas Electronics America, HD64F2636F20J Datasheet - Page 687

• Manufacturer Part Number: HD64F2636F20J
• Description: IC H8S MCU FLASH 128K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2636F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
16.2.13 Interrupt Mask Register (IMR)
The interrupt mask register (IMR) is a 16-bit readable/writable register containing flags that
enable or disable requests by individual interrupt sources.
Bit 15—Overload Frame/Bus Off Recovery Interrupt Mask (IMR7): Enables or disables
overload frame/bus off recovery interrupt requests.
Bit 15: IMR7
0
1
Bit 14—Bus Off Interrupt Mask (IMR6): Enables or disables bus off interrupt requests caused
by the transmit error counter.
Bit 14: IMR6
0
1
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Initial value:
Initial value:
IMR
R/W:
R/W:
Bit:
Bit:
IMR7
Description
Overload frame/bus off recovery interrupt request (OVR0) to CPU by IRR7
enabled
Overload frame/bus off recovery interrupt request (OVR0) to CPU by IRR7
disabled
Description
Bus off interrupt request (ERS0) to CPU by IRR6 enabled
Bus off interrupt request (ERS0) to CPU by IRR6 disabled
R/W
15
—
R
1
7
1
IMR6
R/W
14
—
R
1
6
1
IMR5
R/W
13
—
R
1
5
1
IMR12
IMR4
R/W
R/W
12
1
4
1
IMR3
R/W
11
—
R
Section 16 Controller Area Network (HCAN)
1
3
1
IMR2
R/W
10
—
R
1
2
1
IMR1
IMR9
R/W
R/W
9
1
1
1
(Initial value)
(Initial value)
Page 637 of 1458
IMR8
R/W
—
R
8
0
0
1