HD64F2636F20J Renesas Electronics America, HD64F2636F20J Datasheet - Page 1368
![IC H8S MCU FLASH 128K 128QFP](/photos/28/61/286109/128-bfqfp_sml.jpg)
HD64F2636F20J
Manufacturer Part Number
HD64F2636F20J
Description
IC H8S MCU FLASH 128K 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2636F20J
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
HD64F2636F20J
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HIT
Quantity:
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Part Number:
HD64F2636F20J
Manufacturer:
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Quantity:
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Appendix B Internal I/O Register
LPWRCR—Low-Power Control Register
Page 1318 of 1458
Direct Transition ON Flag
Bit
Initial value
Read/Write
Note:
Note: 1. Bits 7 to 3 in LPWRCR are valid in the U-mask and W-mask versions, and H8S/2635 Group; they are
0
1
• When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts
• When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-sleep mode or
• When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts
• When the SLEEP instruction is executed in sub-active mode, operation shifts directly to high-speed
*
to sleep mode, software standby mode, or watch mode*
watch mode
directly to sub-active mode*, or shifts to sleep mode or software standby mode
mode, or shifts to sub-sleep mode
Always set high-speed mode when shifting to watch mode or sub-active mode.
reserved bits in all other versions.
See sections 23A.2.3, 23B.2.3, Low-Power Control Register (LPWRCR), for more information.
DTON *
Note: * Always set high-speed mode when shifting to watch mode or sub-active mode.
Low-Speed ON Flag
0
1
R/W
7
0
• When the SLEEP instruction is executed in high-speed mode or medium-speed mode,
• When the SLEEP instruction is executed in sub-active mode, operation shifts to watch
• Operation shifts to high-speed mode when watch mode is cancelled
• When the SLEEP instruction is executed in high-speed mode, operation shifts to watch
• When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-
• Operation shifts to sub-active mode when watch mode is cancelled
operation shifts to sleep mode, software standby mode, or watch mode*
mode or shifts directly to high-speed mode
mode or sub-active mode
sleep mode or watch mode
1
LSON *
R/W
6
0
1
Noise Elimination Sampling Frequency Select
0
1
NESEL *
R/W
Sampling using 1/32 × φ
Sampling using 1/4 × φ
5
0
Subclock Enable
0
1
1
SUBSTP *
Enables subclock generation
Disables subclock generation
Oscillation Circuit Feedback Resistance Control Bit
0
1
R/W
4
0
When the main clock is oscillating, sets the feedback
resistance ON. When the main clock is stopped, sets
the feedback resistance OFF
Sets the feedback resistance OFF
1
RFCUT *
R/W
3
0
H'FDEC
1
R/W
⎯
2
0
Frequency Multiplication Factor
0
1
0
1
0
1
STC1
H8S/2639, H8S/2638, H8S/2636,
R/W
×1
×2
×4
Setting prohibited
1
0
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
STC0
R/W
0
0
May 28, 2010
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