C8051F133 Silicon Laboratories Inc, C8051F133 Datasheet - Page 343
C8051F133
Manufacturer Part Number
C8051F133
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F13xr
Specifications of C8051F133
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Data Bus Width
8 bit
Data Ram Size
8.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
32
Number Of Timers
16 bit
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit to 12 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Other names
336-1150
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25.1.1. EXTEST Instruction
The EXTEST instruction is accessed via the IR. The Boundary DR provides control and observability of all
the device pins as well as the Weak Pullup feature. All inputs to on-chip logic are set to logic 1.
25.1.2. SAMPLE Instruction
The SAMPLE instruction is accessed via the IR. The Boundary DR provides observability and presetting of
the scan-path latches.
25.1.3. BYPASS Instruction
The BYPASS instruction is accessed via the IR. It provides access to the standard JTAG Bypass data reg-
ister.
25.1.4. IDCODE Instruction
The IDCODE instruction is accessed via the IR. It provides access to the 32-bit Device ID register.
109, 111, 113, 115,
Version = 0000b
Part Number = 0000 0000 0000 0111b (C8051F120/1/2/3/4/5/6/7 or C8051F130/1/2/3)
Manufacturer ID = 0010 0100 001b (Silicon Labs)
Bit31
103, 105, 107,
124, 126, 128,
125, 127, 129,
118, 120, 122,
119, 121, 123,
130, 132
131, 133
117
Bit
Version
Table 25.1. Boundary Data Register Bit Definitions (Continued)
JTAG Register Definition 25.2. DEVICEID: JTAG Device ID
Bit28 Bit27
Action
Capture P6.n input from pin
Update
Capture P7.n output enable from MCU
Update
Capture P7.n input from pin
Update
Part Number
Target
P6.n output to pin
P7.n output enable to pin
P7.n output to pin
Bit12 Bit11
Rev. 1.4
Manufacturer ID
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Bit1
Bit0
1
0xn0003243
Reset Value
343
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