C8051F133 Silicon Laboratories Inc, C8051F133 Datasheet - Page 204
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C8051F133
Manufacturer Part Number
C8051F133
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F13xr
Specifications of C8051F133
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Data Bus Width
8 bit
Data Ram Size
8.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
32
Number Of Timers
16 bit
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit to 12 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Other names
336-1150
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SILICON
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ST
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C8051F133-GQR
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204
Flash Read Lock Byte
Bits7–0: Each bit locks a corresponding block of memory. (Bit7 is MSB).
Flash Write/Erase Lock Byte
Bits7–0: Each bit locks a corresponding block of memory.
Flash access Limit Register (FLACL)
Read and Write/Erase Security Bits.
(Bit 7 is MSB.)
Bit
7
6
5
4
3
2
1
0
0x1C000 - 0x1FBFD
0x0C000 - 0x0FFFF
0x18000 - 0x1BFFF
0x08000 - 0x0BFFF
0x14000 - 0x17FFF
0x10000 - 0x13FFF
0x04000 - 0x07FFF
0x00000 - 0x03FFF
Memory Block
0: Read operations are locked (disabled) for corresponding block across the JTAG interface.
1: Read operations are unlocked (enabled) for corresponding block across the JTAG inter-
face.
0: Write/Erase operations are locked (disabled) for corresponding block across the JTAG
interface.
1: Write/Erase operations are unlocked (enabled) for corresponding block across the JTAG
interface.
NOTE: When the highest block is locked, the security bytes may be written but not erased.
The Flash Access Limit is defined by the setting of the FLACL register, as described in SFR
Definition 15.1. Firmware running at or above this address is prohibited from using the
MOVX and MOVC instructions to read, write, or erase Flash locations below this address.
Figure 15.2. 128 kB Flash Memory Map and Security Bytes
Write/Erase Lock Byte
Read Lock Byte
Memory Space
Program/Data
SFLE = 0
Reserved
Rev. 1.4
0x1FFFF
0x1FC00
0x1FBFF
0x1FBFE
0x1FBFD
0x00000
Flash Access Limit
Scratchpad Memory
SFLE = 1
(Data only)
0x00FF
0x0000
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