MC68HRC98JK3ECDW Freescale Semiconductor, MC68HRC98JK3ECDW Datasheet - Page 50
![IC MCU 4K FLASH 8MHZ 20-SOIC](/photos/6/50/65027/375-20-soic_sml.jpg)
MC68HRC98JK3ECDW
Manufacturer Part Number
MC68HRC98JK3ECDW
Description
IC MCU 4K FLASH 8MHZ 20-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908JK1ECDWE.pdf
(180 pages)
Specifications of MC68HRC98JK3ECDW
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LED, LVD, POR, PWM
Number Of I /o
15
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 12x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HRC98JK3ECDW
Manufacturer:
MOTOROLA
Quantity:
2 880
Part Number:
MC68HRC98JK3ECDW
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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System Integration Module (SIM)
50
Note: Writing a 0 clears SBSW.
Addr.
$FE00
$FE01
$FE02
$FE03
PIN LOGIC
Register Name
RESET
Break Status Register
Reset Status Register
INTERNAL
PULL-UP
Break Flag Control
Register (BFCR)
V
Reserved
DD
(BSR)
(RSR)
SIM RESET STATUS REGISTER
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
POR:
Figure 5-2. SIM I/O Register Summary
RESET PIN CONTROL
POR CONTROL
MC68HC908JL3E Family Data Sheet, Rev. 4
STOP/WAIT
CONTROL
CONTROL
AND PRIORITY DECODE
INTERRUPT CONTROL
CLOCK
Bit 7
BCFE
Figure 5-1. SIM Block Diagram
POR
R
R
0
1
0
= Unimplemented
PIN
6
R
R
R
0
0
CLOCK GENERATORS
RESET
COUNTER
SIM
÷2
COP
R
R
R
5
0
0
CONTROL
MASTER
RESET
ILOP
4
R
R
R
0
0
ILAD
USB RESET (FROM USB MODULE)
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO OSCILLATOR)
COP CLOCK
2OSCOUT (FROM OSCILLATOR)
OSCOUT (FROM OSCILLATOR)
INTERNAL CLOCKS
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP TIMEOUT (FROM COP MODULE)
INTERRUPT SOURCES
CPU INTERFACE
3
R
R
R
R
0
0
= Reserved
MODRST
2
R
R
R
0
0
Freescale Semiconductor
SBSW
NOTE
LVI
1
R
R
0
0
Bit 0
R
R
R
0
0
0
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