MC68HRC98JK3ECDW Freescale Semiconductor, MC68HRC98JK3ECDW Datasheet - Page 129

IC MCU 4K FLASH 8MHZ 20-SOIC

MC68HRC98JK3ECDW

Manufacturer Part Number
MC68HRC98JK3ECDW
Description
IC MCU 4K FLASH 8MHZ 20-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HRC98JK3ECDW

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LED, LVD, POR, PWM
Number Of I /o
15
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 12x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Connectivity
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HRC98JK3ECDW
Manufacturer:
MOTOROLA
Quantity:
2 880
Part Number:
MC68HRC98JK3ECDW
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Company:
Part Number:
MC68HRC98JK3ECDW
Quantity:
1 437
Chapter 15
Break Module (BREAK)
15.1 Introduction
This section describes the break module. The break module can generate a break interrupt that stops
normal program flow at a defined address to enter a background program.
15.2 Features
Features of the break module include the following:
15.3 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal (BKPT) to the SIM. The SIM then causes the CPU to load the instruction
register with a software interrupt instruction (SWI) after completion of the current CPU instruction. The
program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
When a CPU generated address matches the contents of the break address registers, the break interrupt
begins after the CPU completes its current instruction. A return from interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal operation.
structure of the break module.
Freescale Semiconductor
Accessible I/O registers during the break Interrupt
CPU-generated break interrupts
Software-generated break interrupts
COP disabling during break interrupts
A CPU-generated address (the address in the program counter) matches the contents of the break
address registers.
Software writes a one to the BRKA bit in the break status and control register.
IAB[15:0]
Figure 15-1. Break Module Block Diagram
MC68HC908JL3E Family Data Sheet, Rev. 4
BREAK ADDRESS REGISTER HIGH
BREAK ADDRESS REGISTER LOW
8-BIT COMPARATOR
8-BIT COMPARATOR
IAB[7:0]
IAB[15:8]
CONTROL
Figure 15-1
BKPT
(TO SIM)
shows the
129

Related parts for MC68HRC98JK3ECDW