MC68HC908SR12CB Freescale Semiconductor, MC68HC908SR12CB Datasheet - Page 303

• Manufacturer Part Number: MC68HC908SR12CB
• Description: IC MCU 12K FLASH 8MHZ 42-SDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908SR12CB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, Temp Sensor
• Number Of I /o: 29
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

17.7.3
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
Freescale Semiconductor
MMIIC
Control Register 2 (MMCR2)
Address:
SDASCL1 — SDA and SCL I/O Pin Select
MMALIF — Arbitration Loss Interrupt Flag
MMNAKIF — No AcKnowledge Interrupt Flag (Master Mode)
Reset:
Read: MMALIF MMNAKIF
Write:
This bit selects either SDA0 and SCL0, or SDA1 and SCL1, for MMIIC
I/O pins when MMIIC module is enabled (MMEN = 1). If the SCI
module is enabled (ENSCI = 0), the SDA1 and SCL1 pins are not
available for MMIIC.
Reset clears SDASCL1 bit.
This flag is set when software attempt to set MMAST but the MMBB
has been set by detecting the start condition on the lines or when the
MMIIC is transmitting a "1" to SDA line but detected a "0" from SDA
line in master mode — an arbitration loss. This bit generates an
interrupt request to the CPU if the MMIEN bit in MMCR1 is set. This
bit is cleared by writing "0" to it or by reset.
This flag is only set in master mode (MMAST = 1) when there is no
acknowledge bit detected after one data byte or calling address is
transferred. This flag also clears MMAST. MMNAKIF generates an
interrupt request to CPU if the MMIEN bit in MMCR1 is set. This bit is
cleared by writing "0" to it or by reset.
1 = MMIIC module uses SDA1 and SCL1 I/O pins
0 = MMIIC module uses SDA0 and SCL0 I/O pins
1 = Lost arbitration in master mode
0 = No arbitration lost
1 = No acknowledge bit detected
0 = Acknowledge bit detected
$004A
Bit 7
Figure 17-6. MMIIC Control Register 2 (MMCR2)
Multi-Master IIC Interface (MMIIC)
0
0
= Unimplemented
6
0
0
MMBB
5
0
MMAST
4
0
MMRW
3
0
Multi-Master IIC Interface (MMIIC)
2
0
0
MMIIC I/O Registers
1
0
0
Data Sheet
MMCRCEF
Unaffected
Bit 0
303