MC68HC908SR12CB Freescale Semiconductor, MC68HC908SR12CB Datasheet - Page 296

• Manufacturer Part Number: MC68HC908SR12CB
• Description: IC MCU 12K FLASH 8MHZ 42-SDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908SR12CB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, Temp Sensor
• Number Of I /o: 29
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Multi-Master IIC Interface (MMIIC)
17.6.1 START Signal
17.6.2 Slave Address Transmission
17.6.3 Data Transfer
Data Sheet
296
When the bus is free, (i.e. no master device is engaging the bus — both
SCL and SDA lines are at logic high) a master may initiate
communication by sending a START signal. As shown in
START signal is defined as a high to low transition of SDA while SCL is
high. This signal denotes the beginning of a new data transfer (each data
transfer may contain several bytes of data) and wakes up all slaves.
The first byte transferred immediately after the START signal is the slave
address transmitted by the master. This is a 7-bit calling address
followed by a R/W-bit. The R/W-bit dictates to the slave the desired
direction of the data transfer. A logic 0 indicates that the master wishes
to transmit data to the slave; a logic 1 indicates that the master wishes
to receive data from the slave.
Only the slave with a matched address will respond by sending back an
acknowledge bit by pulling SDA low on the 9th clock cycle.
(See
Once a successful slave addressing is achieved, the data transfer can
proceed byte by byte in the direction specified by the R/W-bit sent by the
calling master.
Each data byte is 8 bits. Data can be changed only when SCL is low and
must be held stable when SCL is high as shown in
MSB is transmitted first and each byte has to be followed by an
acknowledge bit. This is signalled by the receiving device by pulling the
SDA low on the 9th clock cycle. Therefore, one complete data byte
transfer requires 9 clock cycles.
If the slave receiver does not acknowledge the master, the SDA line
should be left high by the slave. The master can then generate a STOP
signal to abort the data transfer or a START signal (repeated START) to
commence a new transfer.
Figure
Multi-Master IIC Interface (MMIIC)
17-2.)
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
Freescale Semiconductor
Figure
Figure
17-2. The
17-2, a