C8051F300 Silicon Laboratories Inc, C8051F300 Datasheet
C8051F300
Specifications of C8051F300
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C8051F300 Summary of contents
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... Can Switch Between Clock Sources on-the-fly; Useful in Power Saving Modes 11-PIN MICRO LEAD PACKAGE - 3x3mm PWB Footprint; Actual MLP Size: ANALOG DIGITAL I/O UART 8-bit SMBus 500ksps PGA PCA ADC Timer 0 Timer 1 TEMP Timer 2 VOLTAGE SENSOR OSCILLATOR 8051 CPU (25MIPS) DEBUG CIRCUITRY 256 B SRAM POR WDT C8051F300/1/2/3/4/5-DS23 ...
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... C8051F300/1/2/3/4/5 2 Notes Rev. 2.3 ...
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... On-Chip Memory ............................................................................................................16 1.3. On-Chip Debug Circuitry ................................................................................................17 1.4. Programmable Digital I/O and Crossbar .........................................................................18 1.5. Serial Ports.......................................................................................................................18 1.6. Programmable Counter Array .........................................................................................19 1.7. 8-Bit Analog to Digital Converter (C8051F300/2 Only) ................................................20 1.8. Comparator ......................................................................................................................21 2. ABSOLUTE MAXIMUM RATINGS ..................................................................................22 3. GLOBAL DC ELECTRICAL CHARACTERISTICS ......................................................23 4. PINOUT AND PACKAGE DEFINITIONS........................................................................24 5 ...
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... C8051F300/1/2/3/4/5 8.3.4. Interrupt Latency....................................................................................................68 8.3.5. Interrupt Register Descriptions ..............................................................................70 8.4. Power Management Modes .............................................................................................75 8.4.1. Idle Mode ...............................................................................................................75 8.4.2. Stop Mode..............................................................................................................75 9. RESET SOURCES ................................................................................................................77 9.1. Power-On Reset...............................................................................................................78 9.2. Power-Fail Reset / VDD Monitor....................................................................................78 9.3. External Reset..................................................................................................................79 9.4. Missing Clock Detector Reset .........................................................................................79 9.5. Comparator0 Reset ..........................................................................................................79 9.6. PCA Watchdog Timer Reset ...........................................................................................79 9 ...
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... Pulse Width Modulator Mode ..................................................................154 16.3.Watchdog Timer Mode..................................................................................................156 16.3.1. Watchdog Timer Operation .................................................................................156 16.3.2. Watchdog Timer Usage .......................................................................................157 16.4. Register Descriptions for PCA ......................................................................................158 17. C2 INTERFACE ..................................................................................................................163 17.1. C2 Interface Registers ...................................................................................................163 17.2.C2 Pin Sharing...............................................................................................................165 C8051F300/1/2/3/4/5 Rev. 2.3 5 ...
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... C8051F300/1/2/3/4/5 6 Notes Rev. 2.3 ...
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... Figure 5.10. ADC Window Compare Examples, Single-Ended Mode ...................................41 Figure 5.11. ADC Window Compare Examples, Differential Mode ......................................42 Figure 5.12. ADC0GT: ADC0 Greater-Than Data Byte Register (C8051F300/2) .................43 Figure 5.13. ADC0LT: ADC0 Less-Than Data Byte Register (C8051F300/2) ......................43 Table 5.1. ADC0 Electrical Characteristics..........................................................................44 6. VOLTAGE REFERENCE (C8051F300/2) Figure 6 ...
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... C8051F300/1/2/3/4/5 7. COMPARATOR0 Figure 7.1. Comparator0 Functional Block Diagram ............................................................47 Figure 7.2. Comparator Hysteresis Plot.................................................................................48 Figure 7.3. CPT0CN: Comparator0 Control Register ...........................................................49 Figure 7.4. CPT0MX: Comparator0 MUX Selection Register..............................................50 Figure 7.5. CPT0MD: Comparator0 Mode Selection Register..............................................51 Table 7.1. Comparator0 Electrical Characteristics...............................................................52 8. CIP-51 MICROCONTROLLER Figure 8 ...
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... Table 14.3. Timer Settings for Standard Baud Rates Using an External Oscillator.............131 Table 14.4. Timer Settings for Standard Baud Rates Using an External Oscillator.............131 Table 14.5. Timer Settings for Standard Baud Rates Using an External Oscillator.............132 Table 14.6. Timer Settings for Standard Baud Rates Using an External Oscillator.............132 15. TIMERS C8051F300/1/2/3/4/5 Rev. 2.3 9 ...
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... C8051F300/1/2/3/4/5 Figure 15.1. T0 Mode 0 Block Diagram................................................................................134 Figure 15.2. T0 Mode 2 Block Diagram................................................................................135 Figure 15.3. T0 Mode 3 Block Diagram................................................................................136 Figure 15.4. TCON: Timer Control Register.........................................................................137 Figure 15.5. TMOD: Timer Mode Register...........................................................................138 Figure 15.6. CKCON: Clock Control Register......................................................................139 Figure 15.7. TL0: Timer 0 Low Byte ....................................................................................140 Figure 15 ...
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... Each device is specified for 2.7 V-to-3.6 V operation over the industrial temperature range (-45°C to +85°C). The Port I/O and /RST pins are tolerant of input signals The C8051F300/1/2/3/4/5 are available in the 11-pin MLP package shown in Figure 4.2. ...
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... C8051F301 25 8k 256 C8051F302 25 8k 256 C8051F303 25 8k 256 C8051F304 25 4k 256 C8051F305 25 2k 256 Figure 1.1. C8051F300/2 Block Diagram Analog/Digital VDD Power GND C2D Debug HW /RST/C2CK Brown- POR Out External XTAL1 Oscillator XTAL2 Circuit System Clock Precision Internal Oscillator 12 ...
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... Figure 1.2. C8051F301/3/4/5 Block Diagram Analog/Digital VDD Power GND C2D Debug HW Reset /RST/C2CK Brown- POR Out External XTAL1 Oscillator XTAL2 Circuit System Clock Precision Internal Oscillator C8051F300/1/2/3/4/5 Port I/O Mode & Config. 8 Port 0 Latch 0 8k/4k/2k byte x2 UART 5 FLASH 1 Timer 0, 1 256 byte SRAM PCA WDT ...
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... CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F300/1/2/3/4/5 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052, including two standard 16-bit ...
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... POR, Reset Input Pin, or FLASH protection may be disabled by the user in software. The WDT may be permanently enabled in software after a power-on reset during MCU initialization. The internal oscillator is available as a factory calibrated 24.5 MHz ±2% (C8051F300/1 devices); an uncalibrated version is available on C8051F302/3/4/5 devices. On all C8051F300/1/2/3/4/5 devices, the internal oscillator period may be user programmed in ~0 ...
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... The first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit addressable. The C8051F300/1/2/3 includes 8k bytes of FLASH program memory (the C8051F304 includes 4k bytes; the C8051F305 includes 2k bytes). This memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip programming voltage ...
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... ADC and SMBus) are stalled when the MCU is halted, during single stepping breakpoint in order to keep them synchronized. The C8051F300DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F300/1/2/3/4/5 MCUs. The kit includes software with a developer's studio and debugger, an integrated 8051 assembler, and an RS-232 to C2 serial adapter ...
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... Programmable Digital I/O and Crossbar C8051F300/1/2/3/4/5 devices include a byte-wide I/O Port that behaves like a typical 8051 Port with a few enhance- ments. Each Port pin may be configured as an analog input or a digital I/O pin. Pins selected as digital I/Os may addi- tionally be configured for push-pull or open-drain output. The “weak pull-ups” that are fixed on typical 8051 devices may be globally disabled, providing power savings capabilities ...
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... WDT mode. The PCA Capture/Compare Module I/O and External Clock Input may be routed to Port I/O via the Digital Crossbar. Figure 1.8. PCA Block Diagram SYSCLK/12 SYSCLK/4 Timer 0 Overflow ECI SYSCLK External Clock/8 Capture/Compare Module 0 C8051F300/1/2/3/4/5 PCA 16-Bit Counter/Timer CLOCK MUX Capture/Compare Module 1 Digital Crossbar Port I/O Rev. 2.3 Capture/Compare ...
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... Analog to Digital Converter (C8051F300/2 Only) The C8051F300/2 includes an on-chip 8-bit SAR ADC with a 10-channel differential input multiplexer and program- mable gain amplifier. With a maximum throughput of 500 ksps, the ADC offers true 8-bit accuracy with an INL of ±1LSB. The ADC system includes a configurable analog multiplexer that selects both positive and negative ADC inputs. Each Port pin is available as an ADC input ...
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... Comparator C8051F300/1/2/3/4/5 devices include an on-chip voltage comparator that is enabled/disabled and configured via user software. All Port I/O pins may be configurated as comparator inputs. Two comparator outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output. Comparator response time is pro- grammable, allowing the user to select between high-speed and low-power modes ...
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... C8051F300/1/2/3/4/5 2. ABSOLUTE MAXIMUM RATINGS Table 2.1. Absolute Maximum Ratings PARAMETER Ambient temperature under bias Storage Temperature Voltage on any Port I/O Pin or /RST with respect to GND Voltage on VDD with respect to GND Maximum Total current through VDD and GND Maximum output current sunk by /RST or any ...
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... Digital Supply RAM Data Retention Voltage Specified Operating Tempera- ture Range SYSCLK (system clock fre- quency) Tsysl (SYSCLK low time) Tsysh (SYSCLK high time) † SYSCLK must be at least 32 kHz to enable debugging. C8051F300/1/2/3/4/5 CONDITIONS MIN 2.7 -40 † Rev. 2.3 TYP ...
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... C8051F300/1/2/3/4/5 4. PINOUT AND PACKAGE DEFINITIONS Table 4.1. Pin Definitions for the C8051F300/1/2/3/4/5 Pin Number Name 1 VREF / P0.0 2 P0.1 3 VDD 4 XTAL1 / P0.2 5 XTAL2 / P0.3 6 P0.4 7 P0.5 8 C2CK / /RST 9 P0.6 / CNVSTR 10 C2D / P0.7 11 GND 24 Type Description A In External Voltage Reference Input. D I/O or Port 0.0. See Section 12 for complete description ...
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... Figure 4.1. MLP-11 Pinout Diagram (Top View) VREF / P0.0 P0.1 VDD XTAL1 / P0.2 XTAL2 / P0.3 C8051F300/1/2/3/4/5 CNVSTR GND Rev. 2.3 C2D / P0.7 P0.6 / C2CK / /RST P0.5 P0.4 25 ...
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... C8051F300/1/2/3/4/5 Figure 4.2. MLP-11 Package Drawing Bottom View Side E View e Side D View e 26 Table 4.2. MLP-11 Package Diminsions E3 MIN 0.09 Rev. 2.3 MM TYP MAX 0.90 1.00 0.02 0.05 0.65 1.00 0.25 0.23 0.30 3.00 2.20 2.25 2.00 0.386 3.00 1 ...
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... Figure 4.3. Typical MLP-11 Solder Mask 0.10 mm 0.35 mm 0.50 mm 0. C8051F300/1/2/3/4 0.50 mm 0.35 mm 0. 0.60 mm 0. Rev. 2.3 0. ...
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... C8051F300/1/2/3/4/5 Figure 4.4. Typical MLP-11 Landing Diagram 0.10 mm 0.35 mm 0.50 mm 0. 0. Rev. 2.3 ...
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... C8051F300/1/2/3/4/5 Notes Rev. 2.3 29 ...
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... C8051F300/1/2/3/4/5 30 Rev. 2.3 ...
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... ADC0 (8-BIT ADC, C8051F300/2) The ADC0 subsystem for the C8051F300/2 consists of two analog multiplexers (referred to collectively as AMUX0) with 11 total input selections, a differential programmable gain amplifier (PGA), and a 500 ksps, 8-bit successive- approximation-register ADC with integrated track-and-hold and programmable window detector (see block diagram in Figure 5 ...
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... C8051F300/1/2/3/4/5 5.1. Analog Multiplexer and PGA The analog multiplexers (AMUX0) select the positive and negative inputs to the PGA, allowing any Port pin to be measured relative to any other Port pin or GND. Additionally, the on-chip temperature sensor or the positive power supply (VDD) may be selected as the positive PGA input. When GND is selected as the negative input, ADC0 operates in Single-ended Mode ...
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... Figure 5.3 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C. Note that parameters which affect ADC measurement, in particular the voltage reference value, will also affect temperature mea- surement. C8051F300/1/2/3/4 3.35*(TEMP ) + 897 mV ...
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... C8051F300/1/2/3/4/5 Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V) 5.00 4.00 3.00 2.00 1.00 0.00 -40.00 -20.00 -1.00 -2.00 -3.00 -4.00 -5.00 34 40.00 0.00 20.00 Temperature (degrees C) Rev. 2.3 5.00 4.00 3.00 2.00 1.00 0.00 60.00 80.00 -1.00 -2.00 -3 ...
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... CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital Crossbar. To configure the Crossbar to skip P0.6, set to ‘1’ Bit6 in register XBR0. See page 95 for details on Port I/O configuration. C8051F300/1/2/3/4/5 Section “15. Timers” on page 133 for timer configuration. Section “12. Port Input/Output” on Rev ...
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... C8051F300/1/2/3/4/5 5.3.2. Tracking Modes The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initiate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR is low ...
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... Differential Mode MUX Select P0 MUX Input MUX SAMPLE P0 MUX MUX Select Note: When the PGA gain is set to 0.5, C C8051F300/1/2/3/4/5 . See Table 5.1 for ADC0 minimum settling time (track/hold time) require × ------ - = TOTAL SAMPLE SA Single-Ended Mode MUX Select P0 ...
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... C8051F300/1/2/3/4/5 Figure 5.6. AMX0SL: AMUX0 Channel Select Register (C8051F300/2) R/W R/W R/W AMX0N3 AMX0N2 AMX0N1 AMX0N0 AMX0P3 Bit7 Bit6 Bit5 Bits7-4: AMX0N3-0: AMUX0 Negative Input Selection. Note that when GND is selected as the Negative Input, ADC0 operates in Single-ended mode. For all other Negative Input selections, ADC0 operates in Differential mode. ...
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... SAR Bit2: UNUSED. Read = 0b; Write = don’t care. Bits1-0: AMP0GN1-0: ADC0 Internal Amplifier Gain (PGA). 00: Gain = 0.5 01: Gain = 1 10: Gain = 2 11: Gain = 4 Figure 5.8. ADC0: ADC0 Data Word Register (C8051F300/2) R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: ADC0 Data Word. ADC0 holds the output data byte from the last ADC0 conversion. When in Single-ended mode, ADC0 holds an 8-bit unsigned integer. When in Differential mode, ADC0 holds a 2’ ...
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... C8051F300/1/2/3/4/5 Figure 5.9. ADC0CN: ADC0 Control Register (C8051F300/2) R/W R/W R/W AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 Bit7 Bit6 Bit5 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for data conversions. Bit6: AD0TM: ADC0 Track Mode Bit ...
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... REF x (255/256) 0xFF AD0WINT not affected 0x21 REF x (32/256) 0x20 0x1F 0x11 REF x (16/256) 0x10 0x0F AD0WINT not affected 0x00 0 C8051F300/1/2/3/4/5 ADC0 Input Voltage (P0.x - GND) REF x (255/256) 0xFF ADC0LT REF x (32/256) 0x1F AD0WINT=1 ADC0GT REF x (16/256) 0x0F 0 Rev. 2.3 AD0WINT=1 ...
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... C8051F300/1/2/3/4/5 5.4.2. Window Detector In Differential Mode Figure 5.11 shows two example window comparisons for differential mode, with ADC0LT = 0x10 (+16d) and ADC0GT = 0xFF (-1d). Notice that in Differential mode, the codes vary from -VREF to VREF*(127/128) and are represented as 8-bit 2’s complement signed integers. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word (ADC0L) is within the range defined by ADC0GT and ADC0LT (if 0xFF (-1d) < ...
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... Figure 5.12. ADC0GT: ADC0 Greater-Than Data Byte Register (C8051F300/2) R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: ADC0 Greater-Than Data Word. Figure 5.13. ADC0LT: ADC0 Less-Than Data Byte Register (C8051F300/2) R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: ADC0 Less-Than Data Word. C8051F300/1/2/3/4/5 ...
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... C8051F300/1/2/3/4/5 Table 5.1. ADC0 Electrical Characteristics VDD = 3.0 V, VREF = 2.40 V (REFSL=0), PGA Gain = 1, -40°C to +85°C unless otherwise specified PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient DYNAMIC PERFORMANCE (10 kHz sine-wave Differential input below Full Scale, 500 ksps) ...
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... Section “12. Port Input/Output” on page 95 nal reference voltage must be within the range 0 ≤ VREF ≤ VDD. On C8051F300/2 devices, the temperature sensor connects to the highest order input of the ADC0 positive input mul- tiplexer (see Section “5.1. Analog Multiplexer and PGA” on page 32 REF0CN enables/disables the temperature sensor ...
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... C8051F300/1/2/3/4/5 Figure 6.2. REF0CN: Reference Control Register R/W R/W R Bit7 Bit6 Bit5 Bits7-3: UNUSED. Read = 00000b; Write = don’t care. Bit3: REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference. 0: VREF input pin used as voltage reference. ...
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... COMPARATOR0 C8051F300/1/2/3/4/5 devices include an on-chip programmable voltage comparator, which is shown in Figure 7.1. Comparator0 offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0 asynchronous “raw” output (CP0A) ...
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... C8051F300/1/2/3/4/5 The output of Comparator0 can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, the Comparator0 output is available asynchronous or synchronous to the system clock; the asyn- chronous output is available even in STOP mode (with no system clock active). When disabled, the Comparator0 out- put (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state, and its supply current falls to less than 100 nA ...
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... Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. Bits1-0: CP0HYN1-0: Comparator0 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. C8051F300/1/2/3/4/5 67). The CP0FIF flag is set to logic 1 R/W R/W R/W CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000 Bit4 ...
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... C8051F300/1/2/3/4/5 Figure 7.4. CPT0MX: Comparator0 MUX Selection Register R/W R/W R CMX0N1 CMX0N0 Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 00b, Write = don’t care. Bits6-4: CMX0N1-CMX0N0: Comparator0 Negative Input MUX Select. These bits select which Port pin is used as the Comparator0 negative input. ...
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... Bit5 Bits7-2: UNUSED. Read = 000000b, Write = don’t care. Bits1-0: CP0MD1-CP0MD0: Comparator0 Mode Select. These bits select the response time for Comparator0. Mode CP0MD1 CP0MD0 CP0 Response Time (TYP C8051F300/1/2/3/4/5 R/W R/W R/W R CP0MD1 Bit4 Bit3 Bit2 Bit1 0 100 ns 1 175 ns ...
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... C8051F300/1/2/3/4/5 Table 7.1. Comparator0 Electrical Characteristics VDD = 3.0 V, -40°C to +85°C unless otherwise specified. PARAMETER CP0+ - CP0- = 100 mV Response Time: † Mode 0, Vcm = 1.5 V CP0+ - CP0- = -100 mV CP0+ - CP0- = 100 mV Response Time: † Mode 1, Vcm = 1.5 V CP0+ - CP0- = -100 mV CP0+ - CP0- = 100 mV Response Time: † ...
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... ACCUMULATOR PSW DATA POINTER PC INCREMENTER PROGRAM COUNTER (PC) PRGM. ADDRESS REG. CONTROL RESET LOGIC CLOCK STOP POWER CONTROL IDLE C8051F300/1/2/3/4/5 Section (Section 8.2.6), and one byte-wide I/O Port (see description - Extended Interrupt Handler - Reset Input - Power Management Modes - On-chip Debug Logic - Program and Data Memory Security ...
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... C8051F300/1/2/3/4/5 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture standard 8051, all instructions except for MUL and DIV take system clock cycles to exe- cute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instruc- tions in one or two system clock cycles, with no instructions taking more than eight system clock cycles ...
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... MOVX Instruction and Program Memory The MOVX instruction is typically used to access external data memory (Note: the C8051F300/1/2/3/4/5 does not support external data or program memory). In the CIP-51, the MOVX instruction accesses the on-chip program mem- ory space implemented as re-programmable FLASH memory ...
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... C8051F300/1/2/3/4/5 Table 8.1. CIP-51 Instruction Set Summary Mnemonic Description MUL AB Multiply A and B DIV AB Divide Decimal adjust A ANL A, Rn AND Register to A ANL A, direct AND direct byte to A ANL A, @Ri AND indirect RAM to A ANL A, #data AND immediate to A ANL direct, A AND A to direct byte ...
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... CJNE A, direct, rel Compare direct byte to A and jump if not equal CJNE A, #data, rel Compare immediate to A and jump if not equal CJNE Rn, #data, rel Compare immediate to Register and jump if not equal C8051F300/1/2/3/4/5 BOOLEAN MANIPULATION PROGRAM BRANCHING Rev. 2.3 Clock Bytes Cycles ...
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... C8051F300/1/2/3/4/5 Table 8.1. CIP-51 Instruction Set Summary Mnemonic Description CJNE @Ri, #data, rel Compare immediate to indirect and jump if not equal DJNZ Rn, rel Decrement Register and jump if not zero DJNZ direct, rel Decrement direct byte and jump if not zero NOP No operation Notes on Registers, Operands and Addressing Modes Register R0-R7 of the currently selected register bank ...
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... The CIP-51 memory organization is shown in Figure 8.2 and Figure 8.3. 8.2.1. Program Memory The CIP-51 core has a 64k-byte program memory space. The C8051F300/1/2/3 implements 8192 bytes of this pro- gram memory space as in-system, re-programmable FLASH memory, organized in a contiguous block from addresses 0x0000 to 0x1FFF ...
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... C8051F300/1/2/3/4/5 8.2.2. Data Memory The CIP-51 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indi- rect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are addres- sable as four banks of general purpose registers, each bank consisting of eight byte-wide registers ...
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... All other SFRs are byte-addressable only. Unoccupied addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate effect and should be avoided. Refer to the corresponding pages of the datasheet, as indicated in Table 8.3, for a detailed description of each register. C8051F300/1/2/3/4/5 Rev. 2.3 61 ...
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... C8051F300/1/2/3/4/5 Table 8.2. Special Function Register (SFR) Memory Map F8 CPT0CN PCA0L PCA0H F0 B P0MDIN E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 E0 ACC XBR0 XBR1 D8 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 D0 PSW REF0CN C8 TMR2CN TMR2RLL TMR2RLH C0 SMB0CN SMB0CF SMB0DAT OSCXCN OSCICN SCON0 SBUF0 90 88 TCON ...
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... Timer/Counter 0 Low TL1 0x8B Timer/Counter 1 Low TMOD 0x89 Timer/Counter Mode TMR2RLH 0xCB Timer/Counter 2 Reload High TMR2RLL 0xCA Timer/Counter 2 Reload Low TMR2H 0xCD Timer/Counter 2 High TMR2L 0xCC Timer/Counter 2 Low C8051F300/1/2/3/4/5 Rev. 2.3 Page 101 101 102 158 159 162 162 162 162 ...
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... C8051F300/1/2/3/4/5 Table 8.3. Special Function Registers Register Address Description XBR0 0xE1 Port I/O Crossbar Control 0 XBR1 0xE2 Port I/O Crossbar Control 1 XBR2 0xE3 Port I/O Crossbar Control 2 0x97, 0xAE, 0xAF, 0xB4, 0xB6, 0xBF, 0xCE, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, Reserved 0xD7, 0xDD, 0xDE, 0xDF, 0xF5 8 ...
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... F1: User Flag 1. This is a bit-addressable, general purpose flag for use under software control. Bit0: PARITY: Parity Flag. This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even. C8051F300/1/2/3/4/5 R/W R/W R/W R/W Bit4 ...
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... C8051F300/1/2/3/4/5 R/W R/W R/W ACC.7 ACC.6 ACC.5 Bit7 Bit6 Bit5 Bits7-0: ACC: Accumulator. This register is the accumulator for arithmetic operations. R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 Bits7- Register. This register serves as a second accumulator for certain arithmetic operations. ...
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... MCU interrupt sources, associated vector addresses, priority order and control bits are summarized in Table 8.4 on page 69. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its inter- rupt-pending flag(s). C8051F300/1/2/3/4/5 Rev. 2.3 67 ...
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... C8051F300/1/2/3/4/5 8.3.2. External Interrupts The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or active low; the IT0 and IT1 bits in TCON (Section “ ...
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... Timer 2 Overflow 0x002B SMBus Interface 0x0033 ADC0 Window Compare 0x003B ADC0 Conversion Complete 0x0043 Programmable Counter Array 0x004B Comparator0 Falling Edge 0x0053 Comparator0 Rising Edge 0x005B C8051F300/1/2/3/4/5 Priority Pending Flag Order Top None N/A N/A 0 IE0 (TCON. TF0 (TCON. IE1 (TCON.3) ...
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... C8051F300/1/2/3/4/5 8.3.5. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). ...
Page 71
... Timer 0 interrupt set to high priority level. Bit0: PX0: External Interrupt 0 Priority Control. This bit sets the priority of the External Interrupt 0 interrupt. 0: External Interrupt 0 priority determined by default priority order. 1: External Interrupt 0 set to high priority level. C8051F300/1/2/3/4/5 R/W R/W R/W R/W PS0 PT1 ...
Page 72
... C8051F300/1/2/3/4/5 Figure 8.12. EIE1: Extended Interrupt Enable 1 R/W R/W R ECP0R Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 00b. Write = don’t care. Bit5: ECP0R: Enable Comparator0 (CP0) Rising Edge Interrupt. This bit sets the masking of the CP0 Rising Edge interrupt. 0: Disable CP0 Rising Edge interrupt. ...
Page 73
... ADC0 Window interrupt set to low priority level. 1: ADC0 Window interrupt set to high priority level. Bit0: PSMB0: SMBus Interrupt Priority Control. This bit sets the priority of the SMBus interrupt. 0: SMBus interrupt set to low priority level. 1: SMBus interrupt set to high priority level. C8051F300/1/2/3/4/5 R/W R/W R/W PCP0F PPCA0 PADC0C ...
Page 74
... C8051F300/1/2/3/4/5 Figure 8.14. IT01CF: INT0/INT1 Configuration Register R/W R/W R/W IN1PL IN1SL2 IN1SL1 Bit7 Bit6 Bit5 Note: Refer to Figure 15.4 for INT0/1 edge- or level-sensitive interrupt selection. Bit7: IN1PL: /INT1 Polarity 0: /INT1 input is active low. 1: /INT1 input is active high. Bits6-4: IN1SL2-0: /INT1 Port Pin Selection Bits These bits select which Port pin is assigned to /INT1. Note that this pin assignment is independent of the Crossbar ...
Page 75
... If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode. The Missing Clock Detector should be disabled if the CPU put to in STOP mode for longer than the MCD timeout of 100 µsec. C8051F300/1/2/3/4/5 for more information on the use and Rev. 2.3 ...
Page 76
... C8051F300/1/2/3/4/5 Figure 8.15. PCON: Power Control Register R/W R/W R/W GF5 GF4 GF3 Bit7 Bit6 Bit5 Bits7-2: GF5-GF0: General Purpose Flags 5-0. These are general purpose flags for use under software control. Bit1: STOP: Stop Mode Select. Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0. ...
Page 77
... Watchdog Timer). Once the system clock source is stable, program execution begins at location 0x0000. Comparator 0 P0.x P0.y Internal Oscillator System Clock External XTAL1 Oscillator XTAL2 Drive Clock Select C8051F300/1/2/3/4/5 for information on selecting and configuring the system clock source. Figure 9.1. Reset Sources VDD Supply Monitor Enable + - Power On Reset + - C0RSEF Missing ...
Page 78
... C8051F300/1/2/3/4/5 9.1. Power-On Reset During power-up, the device is held in a reset state and the /RST pin is driven low until VDD settles above V delay occurs before the device is released from reset; the delay decreases as the VDD ramp time increases (VDD ramp time is defined as how fast VDD ramps from 2.7 V). Figure 9.2. plots the power-on and VDD monitor reset timing. The maximum VDD ramp time ...
Page 79
... A Program read is attempted above user code space. This occurs when user code attempts to branch to an address above the user code space address limit. Table 9.1. User Code Space Address Limits Device C8051F300/1/2/3 C8051F304 C8051F300/1/2/3/4/5 156; the WDT is enabled and User Code Space Address Limit 0x1DFF 0x0FFF Rev. 2.3 ...
Page 80
... C8051F300/1/2/3/4/5 Table 9.1. User Code Space Address Limits Device C8051F305 The FERROR bit (RSTSRC.6) is set following a FLASH error reset. The state of the /RST pin is unaffected by this reset. 9.8. Software Reset Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ following a software forced reset ...
Page 81
... Last reset was not a power-on or VDD monitor reset. 1: Last reset was a power-on or VDD monitor reset; all other reset flags indeterminate. Bit0: PINRSF: HW Pin Reset Flag. 0: Source of last reset was not /RST pin. 1: Source of last reset was /RST pin. C8051F300/1/2/3/4/5 R/W R R/W SWRSF WDTRSF MCDRSF ...
Page 82
... C8051F300/1/2/3/4/5 82 Notes Rev. 2.3 ...
Page 83
... Step 8. Write the first key code to FLKEY: 0xA5. Step 9. Write the second key code to FLKEY: 0xF1. Step 10. Using the MOVX instruction, write a data byte to any location within the 512-byte page to be erased. C8051F300/1/2/3/4/5 Section “17. C2 Interface” on page Rev. 2.3 163. ...
Page 84
... Steps 5-7 must be repeated for each byte to be written. After FLASH writes are complete, PSWE should be cleared so that MOVX instructions do not target program memory. Table 10.1. FLASH Electrical Characteristics PARAMETER CONDITIONS C8051F300/1/2/3 FLASH Size FLASH Size FLASH Size Endurance Erase Cycle Time ...
Page 85
... C2 Device Erase command. Figure 10.1. FLASH Program Memory Map C8051F300/1/2/3 Reserved 0x1E00 Lock Byte 0x1DFF 0x1DFE FLASH memory organized in 512-byte pages 0x0000 C8051F300/1/2/3/4/5 Description C8051F304 Reserved 0x1000 Lock Byte 0x0FFF 0x0FFE FLASH memory organized in 512-byte pages organized in 512-byte 0x0000 Rev ...
Page 86
... C8051F300/1/2/3/4/5 Figure 10.2. PSCTL: Program Store R/W Control R/W R/W R Bit7 Bit6 Bit5 Bits7-2: UNUSED: Read = 000000b, Write = don’t care. Bit1: PSEE: Program Store Erase Enable Setting this bit (in combination with PSWE) allows an entire page of FLASH program memory to be erased. If this bit is logic 1 and FLASH writes are enabled (PSWE is logic 1), a write to FLASH memory using the MOVX instruction will erase the entire page that contains the location addressed by the MOVX instruction ...
Page 87
... This bit enables the 50 ns FLASH read one-shot. When the FLASH one-shot disabled, the FLASH sense amps are enabled for a full clock cycle during FLASH reads. 0: FLASH one-shot disabled. 1: FLASH one-shot enabled. Bits6-0: RESERVED. Read = 0. Must Write 0. C8051F300/1/2/3/4/5 R/W R/W R/W Bit4 Bit3 ...
Page 88
... C8051F300/1/2/3/4/5 88 Notes Rev. 2.3 ...
Page 89
... Programmable Internal Oscillator All C8051F300/1/2/3/4/5 devices include a programmable internal oscillator that defaults as the system clock after a system reset. The internal oscillator period can be adjusted via the OSCICL register as defined by Figure 11.2. On C8051F300/1 devices, OSCICL is factory calibrated to obtain a 24.5 MHz frequency. On C8051F302/3/4/5 devices, the oscillator frequency is a nominal 20 MHz and may vary ± ...
Page 90
... Bits 6-0: OSCICL: Internal Oscillator Calibration Register. This register calibrates the internal oscillator period. The reset value for OSCICL defines the internal oscillator base frequency. On C8051F300/1 devices, the reset value is factory calibrated to generate an internal oscillator frequency of 24.5 MHz. Figure 11.3. OSCICN: Internal Oscillator Control Register ...
Page 91
... To avoid reading a false XTLVLD, in crystal mode software should delay at least 1 ms between enabling the external oscillator and checking XTLVLD. RC and C modes typically require no startup time. C8051F300/1/2/3/4/5 CONDITIONS MIN C8051F300/1 devices 24 C8051F302/3/4/5 devices 16 OSCICN for details on Port input mode selection. ...
Page 92
... C8051F300/1/2/3/4/5 Figure 11.4. OSCXCN: External Oscillator Control Register R R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Bit7 Bit6 Bit5 Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable. 1: Crystal Oscillator is running and stable. Bits6-4: XOSCMD2-0: External Oscillator Mode Bits. ...
Page 93
... Assume VDD = 3.0 V and pF VDD ) = MHz 150 MHz If a frequency of roughly 150 kHz is desired, select the K Factor from the table in Figure 11 22 150 = 0.146 MHz, or 146 kHz Therefore, the XFCN value to use in this example is 011b. C8051F300/1/2/3/4/5 Rev. 2.3 93 ...
Page 94
... C8051F300/1/2/3/4/5 94 Notes Rev. 2.3 ...
Page 95
... CP0 Outputs SYSCLK 4 PCA 2 T0, T1 Lowest Port Latch Priority Figure 12.2. Port I/O Cell Block Diagram /WEAK-PULLUP PUSH-PULL /PORT-OUTENABLE PORT-OUTPUT ANALOG INPUT PORT-INPUT C8051F300/1/2/3/4/5 XBR0, XBR1, P0MDOUT, XBR2 Registers P0MDIN Registers Priority Decoder Digital Crossbar P0 8 I/O Cells 8 P0 (P0.0-P0.7) VDD ...
Page 96
... C8051F300/1/2/3/4/5 12.1. Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 12.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding UART0, which is always at pins 4 and 5 Port pin is assigned, the Crossbar skips that pin when assigning the next selected resource ...
Page 97
... UART TX0 is selected always assigned to P0.4; when UART RX0 is selected always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized functions have been assigned. For example, if assigned functions that take the first 3 Port I/O (P0.[2:0]), 5 Port I/O are left for analog or GPIO use. C8051F300/1/2/3/4 ...
Page 98
... C8051F300/1/2/3/4/5 12.2. Port I/O Initialization Port I/O initialization consists of the following steps: Step 1. Select the input mode (analog or digital) for all Port pins, using the Port0 Input Mode register (P0MDIN). Step 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port0 Output Mode register (P0MDOUT) ...
Page 99
... SDA, SCL routed to Port pins. Bit1: URX0EN: UART RX Enable 0: UART RX0 unavailable at Port pin. 1: UART RX0 routed to Port pin P0.5. Bit0: UTX0EN: UART TX Output Enable 0: UART TX0 unavailable at Port pin. 1: UART TX0 routed to Port pin P0.4. C8051F300/1/2/3/4/5 R/W R/W R/W XSKP4 XSKP3 XSKP2 XSKP1 Bit4 ...
Page 100
... C8051F300/1/2/3/4/5 Figure 12.7. XBR2: Port I/O Crossbar Register 2 R/W R/W R/W WEAKPUD XBARE - Bit7 Bit6 Bit5 Bit7: WEAKPUD: Port I/O Weak Pull-up Disable. 0: Weak Pull-ups enabled (except for Ports whose I/O are configured as push-pull). 1: Weak Pull-ups disabled. Bit6: XBARE: Crossbar Enable. ...
Page 101
... Input Configuration Bits for P0.7-P0.0 (respectively) Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver dis- abled. 0: Corresponding P0.n pin is configured as an analog input. 1: Corresponding P0.n pin is configured as a digital input. C8051F300/1/2/3/4/5 Figure 12.8. P0: Port0 Register R/W R/W R/W P0 ...
Page 102
... C8051F300/1/2/3/4/5 Figure 12.10. P0MDOUT: Port0 Output Mode Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: Output Configuration Bits for P0.7-P0.0 (respectively): ignored if corresponding bit in register P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding P0.n Output is push-pull. (Note: When SDA and SCL appear on any of the Port I/O, each are open-drain regardless of the value of P0MDOUT) ...
Page 103
... SMBUS CONTROL LOGIC Arbitration Interrupt SCL Synchronization Request SCL Generation (Master Mode) SDA Control IRQ Generation C8051F300/1/2/3/4 serial bus. Reads and writes to the interface by the Overflow T1 Overflow 01 TMR2H Overflow 10 TMR2L Overflow 11 FILTER SCL Control Data Path SDA Control Control SMB0DAT FILTER Rev ...
Page 104
... C8051F300/1/2/3/4/5 13.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents The I C-Bus and How to Use It (including specifications), Philips Semiconductor The I C-Bus Specification -- Version 2.0, Philips Semiconductor. 3. System Management Bus Specification -- Version 1.1, SBS Implementers Forum. ...
Page 105
... LOW SDA and lose the arbitration. The winning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. This arbitration scheme is non- destructive: one device always wins, and no data is lost. C8051F300/1/2/3/4/5 SLA5-0 R/W ...
Page 106
... C8051F300/1/2/3/4/5 13.3.2. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I bilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock low period, effectively decreasing the serial clock frequency ...
Page 107
... Slave event enable/disable • Clock source selection These options are selected in the SMB0CF register, as described in ter” on page 108. C8051F300/1/2/3/4/5 for more details on transmission sequences. Section “13.4.2. SMB0CN Control Register” Section “13.4.1. SMBus Configuration Regis- Rev. 2.3 Section 107 ...
Page 108
... C8051F300/1/2/3/4/5 13.4.1. SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the INH bit. With slave events inhib- ited, the SMBus interface will still monitor the SCL and SDA pins ...
Page 109
... SDA and SCL remain high for more than 10 SMBus clock source periods (see Figure 13.4). When a Free Timeout is detected, the interface will respond STOP was detected (an interrupt will be generated, and STO will be set). C8051F300/1/2/3/4/5 Minimum SDA Hold Time - 4 system clocks ...
Page 110
... C8051F300/1/2/3/4/5 Figure 13.5. SMB0CF: SMBus Clock/Configuration Register R/W R/W R ENSMB INH BUSY Bit7 Bit6 Bit5 Bit7: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the interface constantly monitors the SDA and SCL pins. 0: SMBus interface disabled. 1: SMBus interface enabled. ...
Page 111
... Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and the bus is stalled until software clears SI. Table 13.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 13.4 for SMBus status decoding using the SMB0CN register. C8051F300/1/2/3/4/5 Section 13.5.4 for details on this procedure. Rev. 2.3 ...
Page 112
... C8051F300/1/2/3/4/5 Figure 13.6. SMB0CN: SMBus Control Register R R R/W MASTER TXMODE STA Bit7 Bit6 Bit5 Bit7: MASTER: SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 0: SMBus operating in Slave Mode. 1: SMBus operating in Master Mode. Bit6: TXMODE: SMBus Transmit Mode Indicator. ...
Page 113
... SI • A byte has been received. • A START or repeated START followed by a slave address + R/W has been received. • A STOP has been received. C8051F300/1/2/3/4/5 Cleared by Hardware When: • A STOP is generated. • Arbitration is lost. • A START is detected. • Arbitration is lost. • SMB0DAT is not written before the start of an SMBus frame. • ...
Page 114
... C8051F300/1/2/3/4/5 13.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is set. Software should not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register ...
Page 115
... Notice that the ‘data byte transferred’ inter- rupts occur after the ACK cycle in this mode. Figure 13.8. Typical Master Transmitter Sequence S SLA Interrupt Received by SMBus Interface Transmitted by SMBus Interface C8051F300/1/2/3/4 Data Byte A Data Byte Interrupt Interrupt S = START P = STOP ...
Page 116
... C8051F300/1/2/3/4/5 13.5.2. Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more bytes of serial data. After each byte is received, ACKRQ is set to ‘ ...
Page 117
... Notice that the ‘data byte transferred’ interrupts occur before the ACK cycle in this mode. Figure 13.10. Typical Slave Receiver Sequence S SLA W Interrupt Received by SMBus Interface Transmitted by SMBus Interface C8051F300/1/2/3/4/5 A Data Byte A Data Byte Interrupt Interrupt S = START P = STOP A = ACK R = READ SLA = Slave Address Rev ...
Page 118
... C8051F300/1/2/3/4/5 13.5.4. Slave Transmitter Mode Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a slave address and direction bit (READ in this case) is received. Software responds to the received slave address with an ACK, or ignores the received slave address with a NACK ...
Page 119
... ACK received. A master data byte was received; 1000 ACK requested. C8051F300/1/2/3/4/5 TYPICAL RESPONSE OPTIONS Load slave address + R/W into SMB0DAT. Set STA to restart transfer. Abort transfer. Load next data byte into SMB0DAT End transfer with STOP End transfer with STOP and start another transfer ...
Page 120
... C8051F300/1/2/3/4/5 Table 13.4. SMBus Status Decoding VALUES READ CURRENT SMBUS STATE A slave byte was transmitted; NACK received. A slave byte was transmitted; ACK 0100 received. A Slave byte was transmitted; error detected. A STOP was detected while an 0101 addressed Slave Transmitter. 120 TYPICAL RESPONSE ...
Page 121
... A slave byte was received; ACK requested. 0000 Lost arbitration while transmitting data byte as master. C8051F300/1/2/3/4/5 TYPICAL RESPONSE OPTIONS Acknowledge received address (received slave address match, R/W bit = READ). Do not acknowledge received address. Acknowledge received address, and switch to transmitter mode (received slave address match, R/W bit = WRITE) ...
Page 122
... C8051F300/1/2/3/4/5 122 Notes Rev. 2.3 ...
Page 123
... UART0 interrupt (transmit complete or receive complete). Figure 14.1. UART0 Block Diagram Write to SBUF Stop Bit Start Tx Clock UART Baud Rate Generator Rx Clock Start C8051F300/1/2/3/4/5 124). Received data buffering allows UART0 to start reception SFR Bus TB8 SBUF SET (TX Shift CLR Zero Detector ...
Page 124
... C8051F300/1/2/3/4/5 14.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 14.2), which is not user-accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates. The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1) ...
Page 125
... If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set. An interrupt will occur if enabled when either TI0 or RI0 is set. Figure 14.4. 8-Bit UART Timing Diagram MARK START D0 BIT SPACE BIT TIMES BIT SAMPLING C8051F300/1/2/3/4/5 TX RS-232 RS-232 C8051Fxxx LEVEL RX XLTR OR TX ...
Page 126
... C8051F300/1/2/3/4/5 14.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80 (SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in register PSW) for error detection, or used in multiprocessor communications ...
Page 127
... Figure 14.6. UART Multi-Processor Mode Interconnect Diagram Master Slave Device Device C8051F300/1/2/3/4/5 Slave Slave Device Device Rev. 2.3 ...
Page 128
... C8051F300/1/2/3/4/5 Figure 14.7. SCON0: Serial Port 0 Control Register R/W R/W R/W S0MODE - MCE0 Bit7 Bit6 Bit5 Bit7: S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode. 0: Mode 0: 8-bit UART with Variable Baud Rate 1: Mode 1: 9-bit UART with Variable Baud Rate Bit6: UNUSED. Read = 1b. Write = don’ ...
Page 129
... This SFR accesses two registers; a transmit shift register and a receive latch register. When data is written to SBUF0, it goes to the transmit shift register and is held for serial transmission. Writing a byte to SBUF0 is what initiates the transmission. A read of SBUF0 returns the contents of the receive latch. C8051F300/1/2/3/4/5 R/W R/W R/W ...
Page 130
... C8051F300/1/2/3/4/5 Table 14.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator Target Baud Rate Baud Rate % Error (bps) 230400 -0.32% 115200 -0.32% 57600 0.15% 28800 -0.32% 14400 0.15% 9600 -0.32% 2400 -0.32% 1200 0.15 Don’t care † SCA1-SCA0 and T1M bit definitions can be found in Table 14 ...
Page 131
... X = Don’t care † SCA1-SCA0 and T1M bit definitions can be found in C8051F300/1/2/3/4/5 Frequency: 22.1184 MHz Timer Clock SCA1-SCA0 Source (pre-scale select) 96 SYSCLK XX 192 SYSCLK XX 384 SYSCLK XX 768 SYSCLK / 12 ...
Page 132
... C8051F300/1/2/3/4/5 Table 14.5. Timer Settings for Standard Baud Rates Using an External Oscillator Target Baud Rate Baud Rate % Error (bps) 230400 0.00% 115200 0.00% 57600 0.00% 28800 0.00% 14400 0.00% 9600 0.00% 2400 0.00% 1200 0.00% 230400 0.00% 115200 0.00% 57600 0.00% 28800 0 ...
Page 133
... I/O pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock Scale bits in CKCON (see Figure 15.6). C8051F300/1/2/3/4/5 Timer 2 Modes: 16-bit timer with auto-reload Two 8-bit timers with auto-reload Section “ ...
Page 134
... C8051F300/1/2/3/4/5 Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal /INT0 is active as defined by bit IN0PL in register INT01CF (see Figure 8.14). Setting GATE0 to ‘1’ allows the timer to be controlled by the external input signal /INT0 (see facilitating pulse width measurements ...
Page 135
... GATE0 (TMOD.3) is logic 0 or when the input signal /INT0 is active as defined by bit IN0PL in register INT01CF (see external input signals /INT0 and /INT1). Figure 15.2. T0 Mode 2 Block Diagram Pre-scaled Clock SYSCLK T0 Crossbar GATE0 IN0PL XOR /INT0 C8051F300/1/2/3/4/5 Section “8.3.2. External Interrupts” on page 68 CKCON TMOD INT01CF ...
Page 136
... C8051F300/1/2/3/4/5 15.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0 register is restricted to a timer function sourced by the system clock or prescaled clock ...
Page 137
... IT0: Interrupt 0 Type Select. This bit selects whether the configured /INT0 interrupt will be edge or level sensitive. /INT0 is con- figured active low or high by the IN0PL bit in register IT01CF (see Figure 8.14). 0: /INT0 is level triggered. 1: /INT0 is edge triggered. C8051F300/1/2/3/4/5 R/W R/W R/W R/W ...
Page 138
... C8051F300/1/2/3/4/5 Figure 15.5. TMOD: Timer Mode Register R/W R/W R/W GATE1 C/T1 T1M1 Bit7 Bit6 Bit5 Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level. 1: Timer 1 enabled only when TR1 = 1 AND /INT1 is active as defined by bit IN1PL in register INT01CF (see Figure 8 ...
Page 139
... Prescaled Clock Note: External clock divided synchronized with the system clock, and the external clock must be less than or equal to the system clock to operate in this mode. C8051F300/1/2/3/4/5 R/W R/W R/W T1M T0M - Bit4 Bit3 Bit2 System clock divided by 12 System clock divided by 4 ...
Page 140
... C8051F300/1/2/3/4/5 Figure 15.7. TL0: Timer 0 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TL0: Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0 Figure 15.8. TL1: Timer 1 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TL1: Timer 1 Low Byte. ...
Page 141
... Figure 15.11. Timer 2 16-Bit Mode Block Diagram CKCON T2XCLK SYSCLK / External Clock / 8 1 SYSCLK 1 C8051F300/1/2/3/4 SMBus TMR2L Overflow TCLK TR2 TMR2L TMR2H TMR2RLL TMR2RLH Reload Rev. 2.3 To ADC, SMBus TF2H Interrupt TF2L TF2LEN T2SPLIT TR2 T2XCLK 141 ...
Page 142
... C8051F300/1/2/3/4/5 15.2.2. 8-bit Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers operate in auto- reload mode as shown in Figure 15.12. TMR2RLL holds the reload value for TMR2L; TMR2RLH holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is always running when configured for 8-bit Mode ...
Page 143
... T2ML in register CKCON) may still be used to select between the external clock and the system clock for either timer. 0: Timer 2 external clock selection is the system clock divided by 12. 1: Timer 2 external clock selection is the external clock divided by 8. Note that the external oscillator source divided synchronized with the system clock. C8051F300/1/2/3/4/5 R/W R/W R/W R/W ...
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... C8051F300/1/2/3/4/5 Figure 15.14. TMR2RLL: Timer 2 Reload Register Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TMR2RLL: Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the reload value for Timer 2. Figure 15.15. TMR2RLH: Timer 2 Reload Register High Byte ...
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... Access to certain PCA registers is restricted while WDT mode is enabled. See details. Figure 16.1. PCA Block Diagram SYSCLK/12 SYSCLK/4 Timer 0 Overflow ECI SYSCLK External Clock/8 Capture/Compare Module 0 C8051F300/1/2/3/4/5 Section “12.1. Priority Crossbar Decoder” on page 96 PCA 16-Bit Counter/Timer CLOCK MUX Capture/Compare Capture/Compare Module 1 Digital Crossbar Port I/O Rev ...
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... C8051F300/1/2/3/4/5 16.1. PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register. Reading the PCA0L Regis- ter first guarantees an accurate reading of the entire 16-bit PCA0 counter ...
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... X = Don’t Care Figure 16.3. PCA Interrupt Block Diagram (for PCA0CPMn PCA0CN PCA Counter/ Timer Overflow PCA Module 0 (CCF0) PCA Module 1 (CCF1) PCA Module 2 (CCF2) C8051F300/1/2/3/4/5 MAT TOG PWM ECCF Capture triggered by positive edge Capture triggered by negative edge PCA0MD ECCF0 0 1 ECCF1 ...
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... C8051F300/1/2/3/4/5 16.2.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/timer and copy it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transition that triggers the capture: low-to- high transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative edge) ...
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... Writing to PCA0CPLn clears the ECOMn bit to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’. Figure 16.5. PCA Software Timer Mode Diagram Write to 0 PCA0CPLn ENB Reset Write to PCA0CPHn ENB 1 PCA0CPMn C8051F300/1/2/3/4 PCA0CPLn PCA0CPHn Enable 16-bit Comparator PCA PCA0L PCA0H Timebase Rev. 2.3 PCA Interrupt PCA0CN Match 1 149 ...
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... C8051F300/1/2/3/4/5 16.2.3. High Speed Output Mode In High Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn) Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High-Speed Output mode. ...
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... Figure 16.7. PCA Frequency Output Mode Write to 0 PCA0CPLn ENB Reset PCA0CPMn Write PCA0CPHn ENB C8051F300/1/2/3/4/5 F PCA F = ---------------------------------------- - CEXn × 2 PCA0CPHn E C PCA0CPLn 8-bit Adder C F Adder n Enable Toggle x 8-bit match Enable Comparator PCA Timebase PCA0L Rev. 2.3 PCA0CPHn TOGn 0 CEXn Crossbar Port I/O 1 151 ...
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... C8051F300/1/2/3/4/5 16.2.5. 8-Bit Pulse Width Modulator Mode Each module can be used independently to generate a pulse width modulated (PWM) output on its associated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer. The duty cycle of the PWM output signal is varied using the module's PCA0CPLn capture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the value in PCA0CPLn, the output on the CEXn pin will be set to ‘ ...
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... A 0% duty cycle may be generated by clearing the ECOMn bit to ‘0’. Figure 16.8. PCA 8-Bit PWM Mode Diagram Write to 0 PCA0CPLn ENB Reset Write to PCA0CPHn ENB 1 PCA0CPMn C8051F300/1/2/3/4/5 PCA0CPHn PCA0CPLn 8-bit match Enable SET S Comparator R CLR PCA Timebase PCA0L Overflow Rev. 2.3 CEXn Q Crossbar Port I/O Q 153 ...
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... C8051F300/1/2/3/4/5 16.2.6. 16-Bit Pulse Width Modulator Mode A PCA module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare module defines the number of PCA clocks for the low time of the PWM signal. When the PCA counter matches the module contents, the output on CEXn is set to ‘ ...
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... C8051F300/1/2/3/4/5 Rev. 2.3 155 ...
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... C8051F300/1/2/3/4/5 16.3. Watchdog Timer Mode A programmable watchdog timer (WDT) function is available through the PCA Module 2. The WDT is used to gen- erate a reset if the time between writes to the WDT update register (PCA0CPH2) exceed a specified limit. The WDT can be configured and enabled/disabled as needed by software. ...
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... Assumes SYSCLK / 12 as the PCA clock source, and a PCA0L value of 0x00 at the update time. †† Internal oscillator reset frequency. C8051F300/1/2/3/4/5 ( × 256 PCA0CPL2 + 256 PCA0L – PCA0CPL2 255 128 32 ...
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... C8051F300/1/2/3/4/5 16.4. Register Descriptions for PCA Following are detailed descriptions of the special function registers related to the operation of the PCA. Figure 16.11. PCA0CN: PCA Control Register R/W R/W R Bit7 Bit6 Bit5 Bit7: CF: PCA Counter/Timer Overflow Flag. Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000. When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine ...
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... Disable the CF interrupt. 1: Enable a PCA Counter/Timer Overflow interrupt when CF (PCA0CN.7) is set. Note: When the WDTE bit is set to ‘1’, the PCA0MD register cannot be modified. To change the contents of the PCA0MD register, the Watchdog Timer must first be disabled. C8051F300/1/2/3/4/5 R/W R/W R/W R/W ...
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... C8051F300/1/2/3/4/5 Figure 16.13. PCA0CPMn: PCA Capture/Compare Mode Registers R/W R/W R/W PWM16n ECOMn CAPPn Bit7 Bit6 Bit5 PCA0CPMn Address: PCA0CPM0 = 0xDA ( PCA0CPM1 = 0xDB ( PCA0CPM2 = 0xDC ( Bit7: PWM16n: 16-bit Pulse Width Modulation Enable. This bit selects 16-bit mode when Pulse Width Modulation mode is enabled (PWMn = 1). ...
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... Figure 16.15. PCA0H: PCA Counter/Timer High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: PCA0H: PCA Counter/Timer High Byte. The PCA0H register holds the high byte (MSB) of the 16-bit PCA Counter/Timer. C8051F300/1/2/3/4/5 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 ...
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... C8051F300/1/2/3/4/5 Figure 16.16. PCA0CPLn: PCA Capture Module Low Byte R/W R/W R/W Bit7 Bit6 Bit5 PCA0CPLn Address: PCA0CPL0 = 0xFB ( PCA0CPL1 = 0xE9 ( PCA0CPL2 = 0xEB ( Bits7-0: PCA0CPLn: PCA Capture Module Low Byte. The PCA0CPLn register holds the low byte (LSB) of the 16-bit capture Module n. ...
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... C2 INTERFACE C8051F300/1/2/3/4/5 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow FLASH pro- gramming, boundary scan functions, and in-system debugging with the production part installed in the end applica- tion. The C2 interface operates similar to JTAG, where the three JTAG data signals (TDI, TDO, TMS) are mapped into one bi-directional C2 data signal (C2D) ...
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... C8051F300/1/2/3/4/5 Figure 17.3. REVID: C2 Revision ID Register Bit7 Bit6 Bit5 This read-only register returns the 8-bit revision ID: 0x00 (Revision A) Figure 17.4. FPCTL: C2 FLASH Programming Control Register Bit7 Bit6 Bit5 Bits7-0 FPCTL: FLASH Programming Control Register This register is used to enable FLASH programming via the C2 interface. To enable C2 FLASH programming, the following codes must be written in order: 0x02, 0x01 ...
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... The configuration in Figure 17.6 assumes the following: 1. The user input (b) cannot change state while the target device is halted. 2. The /RST pin on the target device is used as an input only. Additional resistors may be necessary depending on the specific application. C8051F300/1/2/3/4/5 C8051F300 C2CK (/RST) C2D (P0.7) Rev. 2.3 165 ...
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... C8051F300/1/2/3/4/5 Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein ...