MC68HC908AP64CB Freescale Semiconductor, MC68HC908AP64CB Datasheet - Page 174

• Manufacturer Part Number: MC68HC908AP64CB
• Description: IC MCU 64K FLASH 8MHZ 42SDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AP64CB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SCI, SPI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 30
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• For Use With: DEMO908AP64E - BOARD DEMO FOR 908AP64DEMO908AP64 - BOARD DEMO FOR 908AP64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Serial Communications Interface Module (SCI)
NEIE — Receiver Noise Error Interrupt Enable Bit
FEIE — Receiver Framing Error Interrupt Enable Bit
PEIE — Receiver Parity Error Interrupt Enable Bit
11.8.4 SCI Status Register 1
SCI status register 1 (SCS1) contains flags to signal these conditions:
SCTE — SCI Transmitter Empty Bit
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This read/write bit enables SCI error CPU interrupt requests generated by the noise error bit, NE.
Reset clears NEIE.
This read/write bit enables SCI error CPU interrupt requests generated by the framing error bit, FE.
Reset clears FEIE.
This read/write bit enables SCI error CPU interrupt
requests generated by the parity error bit, PE. (See
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This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register.
SCTE can generate an SCI transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,
SCTE generates an SCI transmitter CPU interrupt request. In normal operation, clear the SCTE bit by
reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit.
1 = SCI error CPU interrupt requests from NE bit enabled
0 = SCI error CPU interrupt requests from NE bit disabled
1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
Transfer of SCDR data to transmit shift register complete
Transmission complete
Transfer of receive shift register data to SCDR complete
Receiver input idle
Receiver overrun
Noisy data
Framing error
Parity error
Address:
Reset:
Read:
Write:
$0016
SCTE
Bit 7
1
Figure 11-12. SCI Status Register 1 (SCS1)
= Unimplemented
TC
6
1
MC68HC908AP Family Data Sheet, Rev. 4
SCRF
5
0
IDLE
4
0
11.8.4 SCI Status Register
OR
3
0
NF
2
0
FE
1
0
1.) Reset clears PEIE.
Freescale Semiconductor
Bit 0
PE
0