MC68HC908GZ8VFA Freescale Semiconductor, MC68HC908GZ8VFA Datasheet - Page 53

• Manufacturer Part Number: MC68HC908GZ8VFA
• Description: IC MCU 8K FLASH 8MHZ CAN 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GZ8VFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

3.7.4 ADC Voltage Reference Low Pin (V
The ADC analog portion uses V
to the same voltage potential as V
results. Any noise present on this pin will be reflected and possibly magnified in A/D conversion values.
V
3.7.5 ADC Voltage In (V
V
3.8 I/O Registers
These I/O registers control and monitor ADC operation:
3.8.1 ADC Status and Control Register
Function of the ADC status and control register (ADSCR) is described here.
COCO — Conversions Complete Bit
AIEN — ADC Interrupt Enable Bit
Freescale Semiconductor
SSAD
ADIN
•
•
•
In non-interrupt mode (AIEN = 0), COCO is a read-only bit that is set at the end of each conversion.
COCO will stay set until cleared by a read of the ADC data register. Reset clears this bit.
In interrupt mode (AIEN = 1), COCO is a read-only bit that is not set at the end of a conversion. It
always reads as a logic 0.
When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is
cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0) or CPU interrupt enabled (AIEN = 1)
1 = ADC interrupt enabled
0 = ADC interrupt disabled
is the input voltage signal from one of the eight ADC channels to the ADC module.
ADC status and control register (ADSCR)
ADC data register (ADRH and ADRL)
ADC clock register (ADCLK)
and V
REFL
Address:
For maximum noise immunity, route V
to V
Routing V
noise rejection.
Reset:
Read:
Write:
are double-bonded on the MC68HC908GZ16.
SS
, place bypass capacitors as close as possible to the package.
$003C
COCO
Figure 3-4. ADC Status and Control Register (ADSCR)
Bit 7
REFH
0
ADIN
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
close and parallel to V
REFL
AIEN
)
SS
6
0
. External filtering is often necessary to ensure a clean V
as its lower voltage reference pin. By default, connect the V
ADCO
5
0
REFL
NOTE
ADCH4
4
1
REFL
)
REFL
may improve common mode
carefully and, if not connected
ADCH3
3
1
ADCH2
2
1
ADCH1
1
1
ADCH0
Bit 0
1
REFL
I/O Registers
REFH
for good
pin
53