MC68HC908GZ8VFA Freescale Semiconductor, MC68HC908GZ8VFA Datasheet - Page 215

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MC68HC908GZ8VFA

Manufacturer Part Number
MC68HC908GZ8VFA
Description
IC MCU 8K FLASH 8MHZ CAN 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908GZ8VFA

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC908GZ8VFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
16.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in
originates from either an external oscillator or from the on-chip PLL.
16.2.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four
or the PLL output (CGMVCLK) divided by four.
16.2.2 Clock Startup from POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR
timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks
start upon completion of the timeout.
16.2.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt or reset, the SIM allows CGMXCLK to clock the SIM counter.
The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is
selectable as 4096 or 32 CGMXCLK cycles. See
In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules.
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
Freescale Semiconductor
OSCENINSTOP
CONFIG
FROM
OSC2
OSC1
PHASE-LOCKED LOOP (PLL)
CGMRCLK
OSCILLATOR (OSC)
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Figure 16-3. System Clock Signals
CGMXCLK
CGMOUT
16.6.2 Stop Mode.
÷ 2
SIM COUNTER
TO MSCAN
TO TBM,TIM1,TIM2, ADC, MSCAN
SIM Bus Clock Control and Generation
SIM
GENERATORS
BUS CLOCK
Figure
16-3. This clock
SIMOSCEN
IT12
TO REST
OF CHIP
IT23
TO REST
OF CHIP
215

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