MC68HC908GZ8VFA Freescale Semiconductor, MC68HC908GZ8VFA Datasheet - Page 118

• Manufacturer Part Number: MC68HC908GZ8VFA
• Description: IC MCU 8K FLASH 8MHZ CAN 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GZ8VFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Low-Voltage Inhibit (LVI)
LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration register (CONFIG1). See
Figure 5-2. Configuration Register 1 (CONFIG1)
reset occurs, the MCU remains in reset until V
to exit reset. See
and the LVI. The output of the comparator controls the state of the LVIOUT flag in the LVI status register
(LVISR).
An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
11.3.1 Polled LVI Operation
In applications that can operate at V
the LVIOUT bit. In the configuration register, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
11.3.2 Forced Reset Operation
In applications that require V
module to reset the MCU when V
LVIPWRD and LVIRSTD bits must be at logic 0 to enable the LVI module and to enable LVI resets.
118
Addr.
$FE0C
Register Name
LVI Status Register
See page 119.
16.3.2.5 Low-Voltage Inhibit (LVI) Reset
FROM CONFIG1
DETECTOR
(LVISR)
LOW V
LVI5OR3
V
DD
DD
Reset:
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Read:
Write:
DD
Figure 11-1. LVI Module Block Diagram
Figure 11-2. LVI I/O Register Summary
to remain above the V
V
V
DD
DD
DD
LVIOUT
FROM CONFIG
> LVI
≤ LVI
Bit 7
DD
LVIPWRD
falls below the V
0
Trip
Trip
levels below the V
= 0
= 1
= Unimplemented
6
0
0
DD
for details of the LVI’s configuration bits. Once an LVI
LVIOUT
rises above a voltage, V
TRIPF
TRIPF
5
0
0
STOP INSTRUCTION
FROM CONFIG1
TRIPF
for details of the interaction between the SIM
level. In the configuration register, the
LVIRSTD
level, enabling LVI resets allows the LVI
level, software can monitor V
4
0
0
3
0
0
TRIPR
FROM CONFIG1
LVISTOP
LVI RESET
, which causes the MCU
2
0
0
Freescale Semiconductor
1
0
0
DD
by polling
Bit 0
0
0