MC68HC908MR8CP Freescale Semiconductor, MC68HC908MR8CP Datasheet - Page 243

• Manufacturer Part Number: MC68HC908MR8CP
• Description: IC MCU 8K FLASH 8MHZ PWM 28-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908MR8CP

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 12
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
NOTE:
CHxIE — Channel x Interrupt Enable Bit
MSxB — Mode Select Bit B
MSxA — Mode Select Bit A
Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIMB status and control register
(TBSC).
When CHxIE = 1, clear CHxF by reading TIMB channel x status and
control register with CHxF set, and then writing a logic 0 to CHxF. If
another interrupt request occurs before the clearing sequence is
complete, then writing logic 0 to CHxF has no effect. Therefore, an
interrupt request cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
This read/write bit enables TIMB CPU interrupts on channel x. Reset
clears the CHxIE bit.
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIMB channel 0. Reset clears the MSxB bit.
When ELSxB:A ≠ 00, this read/write bit selects either input capture
operation or unbuffered output compare/PWM operation. See
Table
When ELSxB:A = 00, this read/write bit selects the initial output level
of the TCHx pin once PWM, input capture, or output compare
operation is enabled. Reset clears the MSxA bit. See
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
1 = Initial output level low
0 = Initial output level high
12-2.
Timer Interface B (TIMB)
Timer Interface B (TIMB)
Table
Technical Data
I/O Registers
12-2.
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