MC68HC908GR8CP Freescale Semiconductor, MC68HC908GR8CP Datasheet - Page 71

• Manufacturer Part Number: MC68HC908GR8CP
• Description: IC MCU FLASH 8BIT 8MHZ 4K 28-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GR8CP

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 17
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

4.4.2.1 SWI Instruction
4.4.2.2 Break Interrupt
4.4.2.3 IRQ Pin
4.4.2.4 CGM
4.4.2.5 TIM1
MC68HC908GR8 — Rev 4.0
MOTOROLA
NOTE:
The software interrupt instruction (SWI) causes a non-maskable
interrupt.
A software interrupt pushes PC onto the stack. An SWI does not push
PC – 1, as a hardware interrupt does.
The break module causes the CPU to execute an SWI instruction at a
software-programmable break point.
A logic 0 on the IRQ1 pin latches an external interrupt request.
The CGM can generate a CPU interrupt request every time the phase-
locked loop circuit (PLL) enters or leaves the locked state. When the
LOCK bit changes state, the PLL flag (PLLF) is set. The PLL interrupt
enable bit (PLLIE) enables PLLF CPU interrupt requests. LOCK is in the
PLL bandwidth control register. PLLF is in the PLL control register.
TIM1 CPU interrupt sources:
Freescale Semiconductor, Inc.
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For More Information On This Product,
TIM1 overflow flag (TOF) — The TOF bit is set when the TIM1
counter value rolls over to $0000 after matching the value in the
TIM1 counter modulo registers. The TIM1 overflow interrupt
enable bit, TOIE, enables TIM1 overflow CPU interrupt requests.
TOF and TOIE are in the TIM1 status and control register.
TIM1 channel flags (CH1F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. The channel
x interrupt enable bit, CHxIE, enables channel x TIM1 CPU
interrupt requests. CHxF and CHxIE are in the TIM1 channel x
status and control register.
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Resets and Interrupts
Resets and Interrupts
Technical Data
Interrupts
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