MC68HC908GR8CP Freescale Semiconductor, MC68HC908GR8CP Datasheet - Page 309

• Manufacturer Part Number: MC68HC908GR8CP
• Description: IC MCU FLASH 8BIT 8MHZ 4K 28-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GR8CP

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 17
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

20.7 Queuing Transmission Data
MC68HC908GR8 — Rev 4.0
MOTOROLA
The double-buffered transmit data register allows a data byte to be
queued and transmitted. For an SPI configured as a master, a queued
data byte is transmitted immediately after the previous transmission has
completed. The SPI transmitter empty flag (SPTE) indicates when the
transmit data buffer is ready to accept new data. Write to the transmit
data register only when the SPTE bit is high.
timing associated with doing back-to-back transmissions with the SPI
(SPSCK has CPHA: CPOL = 1:0).
The transmit data buffer allows back-to-back transmissions without the
slave precisely timing its writes between transmissions as in a system
with a single data buffer. Also, if no new data is written to the data buffer,
the last value contained in the shift register is the next data word to be
transmitted.
CPHA:CPOL = 1:0
WRITE TO SPDR
1
2
3
4 FIRST INCOMING BYTE TRANSFERS FROM SHIFT
5
6 CPU READS SPSCR WITH SPRF BIT SET.
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READ SPSCR
CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT.
BYTE 1 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2
AND CLEARING SPTE BIT.
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
READ SPDR
For More Information On This Product,
SPSCK
SPRF
SPTE
MOSI
Serial Peripheral Interface (SPI)
Figure 20-8. .SPRF/SPTE CPU Interrupt Timing
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1
MSB BIT
BYTE 1
2
6
BIT
5
3
BIT
4
BIT
3
BIT
2
BIT
1
11 CPU READS SPSCR WITH SPRF BIT SET.
12 CPU READS SPDR, CLEARING SPRF BIT.
10
7 CPU READS SPDR, CLEARING SPRF BIT.
8
9
LSB MSB BIT
5
4
CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE
3 AND CLEARING SPTE BIT.
SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
BYTE 2
6
Serial Peripheral Interface (SPI)
Figure 20-8
6
7
BIT
Queuing Transmission Data
5
8
BIT
4
BIT
3
BIT
2
BIT
shows the
1
Technical Data
LSB MSB BIT
10
9
BYTE 3
11
6
12
BIT
5
309
BIT
4