MC68HC11F1CFN4 Freescale Semiconductor, MC68HC11F1CFN4 Datasheet - Page 54

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MC68HC11F1CFN4

Manufacturer Part Number
MC68HC11F1CFN4
Description
IC MCU 512 EEPROM 4MHZ 68-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC11F1CFN4

Core Processor
HC11
Core Size
8-Bit
Speed
4MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
30
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.25 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
68-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Program Memory Size
-

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11.1 Input Pins
11.2 Conversion Sequence
54
E CLOCK
Port E pins can also be used as digital inputs. Reads of port E pins are not recommended during the
sample portion of an A/D conversion cycle, when the gate signal to the N-channel input gate is on. Be-
cause no P-channel devices are directly connected to either input pins or reference voltage pins, volt-
ages above V
maximum ratings. Figure 15 is a functional diagram of an input pin.
A/D converter operations are performed in sequences of four conversions each. A conversion sequence
can be repeated continuously or stop after one iteration. The conversion complete flag (CCF) is set after
the fourth conversion in a sequence to show the availability of data in the result registers. Figure 16
shows the timing of a typical sequence. Synchronization is referenced to the system E clock.
0
ANALOG
INPUT
* THIS ANALOG SWITCH IS CLOSED ONLY DURING THE 12-CYCLE SAMPLE TIME.
CHANNEL, UPDATE
PIN
CONVERT FIRST
SAMPLE ANALOG INPUT
ADR1
Figure 15 Electrical Model of an Analog Input Pin (Sample Mode)
DD
12 E CYCLES
PROTECTION
do not cause a latchup problem, although current should be limited according to
< 2 pF
DEVICE
INPUT
Freescale Semiconductor, Inc.
32
For More Information On This Product,
+ ~20V
– ~0.7V
CONVERT SECOND
CHANNEL, UPDATE
Figure 16 A/D Conversion Sequence
ADR2
Go to: www.freescale.com
CYCLES
MSB
4
DUMMY N-CHANNEL
SUCCESSIVE APPROXIMATION SEQUENCE
+ ~12V
– ~0.7V
OUTPUT DEVICE
BIT 6
CYC
64
2
CHANNEL, UPDATE
BIT 5
CYC
CONVERT THIRD
2
BIT 4
CYC
ADR3
2
BIT 3
CYC
2
BIT 2
CYC
DIFFUSION/POLY
2
JUNCTION
LEAKAGE
96
400 nA
COUPLER
BIT 1
CYC
CONVERT FOURTH
CHANNEL, UPDATE
2
4 K
CYC
LSB
ADR4
2
CYC
END
~ 20 pF
2
MC68HC11F1/FC0
*
MC68HC11FTS/D
128 — E CYCLES
CAPACITANCE
V
RL
DAC

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