MC68HC11F1CFN4 Freescale Semiconductor, MC68HC11F1CFN4 Datasheet - Page 12

• Manufacturer Part Number: MC68HC11F1CFN4
• Description: IC MCU 512 EEPROM 4MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11F1CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -

2.3 Pin Descriptions
12
V
RESET
XTAL and EXTAL
E
DS
WAIT
4XOUT
IRQ
XIRQ
MODA/LIR and MODB/VSTBY
R/W
V
DD
RH
V
This active-low input initializes the MCU to a known startup state. It also acts as an open-drain
output to indicate that an internal failure has been detected in either the clock monitor or the COP
watchdog circuits.
These two pins provide the interface for either a crystal or a CMOS-compatible clock to drive the
internal clock circuitry. The frequency applied to these pins is four times the desired bus
frequency (E clock).
This pin provides an output for the E clock, the basic timing reference signal for the bus circuitry.
The address bus is active when E is low, and the data bus is active when E is high.
The data strobe output is the inverted E clock. DS is present on the MC68HC11FC0 only.
This input is used to stretch the bus cycle to accomodate slower devices. The MCU samples the
logic level at this pin on the rising edge of E clock. If it is high, the MCU holds the E clock high for
the next four EXTAL clock cycles. If it is low, the E clock responds normally, going low two
EXTAL cycles later. The WAIT pin is present on the MC68HC11FC0 only.
This pin provides a buffered oscillator signal to drive another M68HC11 MCU. The 4XOUT pin is
not present on the 64-pin QFP MC68HC11FC0 package.
This active-low input provides a means of generating asynchronous, maskable interrupt requests
for the CPU.
This interrupt request input can be made non-maskable by clearing the X bit in the MCU’s
condition code register.
The logic level applied to the MODA and MODB pins at reset determines the MCU’s opreating
mode (see Table 7 in 4 Operating Modes and System Initialization). After reset, MODA
functions as LIR, an open-drain output that indicates the start of an instruction cycle. MODB
functions as V
In expanded and test modes, R/W indicates the direction of transfers on the external data bus.
These pins provide the reference voltage for the analog-to-digital converter. Use bypass
capacitors to minimize noise on these signals. Any noise on V
accuracy. These pins are not present on the MC68HC11FC0.
and V
and V
DD
is the positive power input to the MCU, and V
SS
RL
STBY
, providing a backup battery to maintain the contents of RAM when V
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SS
is ground.
RH
and V
RL
will directly affect A/D
MC68HC11F1/FC0
MC68HC11FTS/D
DD
falls.